公开(公告)号：US09030341B2

公开(公告)日：2015-05-12

申请号：US13553017

申请日：2012-07-19

申请人： Loke Tan ,  Steven Jaffe ,  Hong Liu ,  Lin He ,  Randall Perlow ,  Peter Cangiane ,  Ramon Gomez ,  Giuseppe Cusmai

发明人： Loke Tan ,  Steven Jaffe ,  Hong Liu ,  Lin He ,  Randall Perlow ,  Peter Cangiane ,  Ramon Gomez ,  Giuseppe Cusmai

IPC分类号： H03M1/10 ,  H03M1/12

CPC分类号： H03M1/1052 ,  H03M1/1215

摘要： Various multi-lane ADCs are disclosed that substantially compensate for impairments present within various signals that result from various impairments, such as phase offset, amplitude offset, and/or DC offset to provide some examples, such that their respective digital output samples accurately represent their respective analog inputs. Generally, the various multi-lane ADCs determine various statistical relationships, such as various correlations to provide an example, between these various signals and various known calibration signals to quantify the phase offset, amplitude offset, and/or DC offset that may be present within the various signals. The various multi-lane ADCs adjust the various signals to substantially compensate for the phase offset, amplitude offset, and/or DC offset based upon these various statistical relationships such that their respective digital output samples accurately represent their respective analog inputs.

摘要翻译： 公开了各种多通道ADC，其基本上补偿由各种损伤（例如相位偏移，幅度偏移和/或DC偏移）导致的各种信号内存在的损伤，以提供一些示例，使得它们各自的数字输出样本准确地表示它们 各自的模拟输入。 通常，各种多通道ADC确定各种统计关系，例如各种相关性，以提供这些各种信号之间的示例，以及各种已知的校准信号，以量化可能存在的相位偏移，幅度偏移和/或DC偏移 各种信号。 各种多通道ADC基于这些各种统计关系调整各种信号以基本上补偿相位偏移，幅度偏移和/或DC偏移，使得它们各自的数字输出样本精确地表示它们各自的模拟输入。

公开(公告)号：US20140002284A1

公开(公告)日：2014-01-02

申请号：US13553017

申请日：2012-07-19

申请人： Loke TAN ,  Steven Jaffe ,  Hong Liu ,  Lin He ,  Randall Perlow ,  Peter Cangiane ,  Ramon Gomez ,  Giuseppe Cusmai

发明人： Loke TAN ,  Steven Jaffe ,  Hong Liu ,  Lin He ,  Randall Perlow ,  Peter Cangiane ,  Ramon Gomez ,  Giuseppe Cusmai

IPC分类号： H03M1/06

CPC分类号： H03M1/1052 ,  H03M1/1215

摘要： Various multi-lane ADCs are disclosed that substantially compensate for impairments present within various signals that result from various impairments, such as phase offset, amplitude offset, and/or DC offset to provide some examples, such that their respective digital output samples accurately represent their respective analog inputs. Generally, the various multi-lane ADCs determine various statistical relationships, such as various correlations to provide an example, between these various signals and various known calibration signals to quantify the phase offset, amplitude offset, and/or DC offset that may be present within the various signals. The various multi-lane ADCs adjust the various signals to substantially compensate for the phase offset, amplitude offset, and/or DC offset based upon these various statistical relationships such that their respective digital output samples accurately represent their respective analog inputs.

摘要翻译： 公开了各种多通道ADC，其基本上补偿由各种损伤产生的各种信号中存在的损伤，例如相位偏移，幅度偏移和/或DC偏移，以提供一些示例，使得它们各自的数字输出样本准确地表示它们 各自的模拟输入。 通常，各种多通道ADC确定各种统计关系，例如各种相关性，以提供这些各种信号之间的示例，以及各种已知的校准信号，以量化可能存在的相位偏移，幅度偏移和/或DC偏移 各种信号。 各种多通道ADC基于这些各种统计关系调整各种信号以基本上补偿相位偏移，幅度偏移和/或DC偏移，使得它们各自的数字输出样本精确地表示它们各自的模拟输入。

公开(公告)号：US5329473A

公开(公告)日：1994-07-12

申请号：US761088

申请日：1991-09-17

申请人： Peter Cangiane

发明人： Peter Cangiane

IPC分类号： G06F17/14 ,  G06F15/332

CPC分类号： G06F17/142

摘要： An architecture and method for performing the known windowing and presumming operations associated with enhancing the performance of a fast Fourier transform (FFT) processor is disclosed. The method makes use of a reordering process in order to enable the multiplying and accumulating processes associated with the windowing and presumming operations to be performed on consecutive data points. In order to apply the appropriate coefficients to the multiplier, coefficients are loaded into a series of registers in a loop configuration in which the coefficient in one register is transferred to an adjacent register upon every clock cycle and the last coefficient register transfers its coefficient to the first register. An accumulator accumulates output from the multiplier and applies it to a delay register. The procedure of accumulating consecutive data points enables a delay register to be used in place of the prior art delay memories, thus enabling specialized chips to be effectively implemented without any random access memory (RAM). Consequently, efficient utilization of specialized integrated chips and memories is attainable.

摘要翻译： 公开了一种用于执行与提高快速傅里叶变换（FFT）处理器的性能相关联的已知加窗和推测操作的架构和方法。 该方法利用重新排序过程，以便能够对连续数据点执行与加窗和推测操作相关联的乘法和累积处理。 为了将适当的系数应用到乘法器，将系数以循环配置加载到一系列寄存器中，其中在每个时钟周期将一个寄存器中的系数传送到相邻寄存器，并且最后一个系数寄存器将其系数传送到 首先注册 累加器从乘法器累加输出并将其应用于延迟寄存器。 累积连续数据点的过程使得可以使用延迟寄存器来代替现有技术的延迟存储器，从而使得能够有效地实现专用芯片而不需要任何随机存取存储器（RAM）。 因此，可以实现专用集成芯片和存储器的有效利用。