公开(公告)号：US11677409B2

公开(公告)日：2023-06-13

申请号：US17368807

申请日：2021-07-06

申请人： Microsoft Technology Licensing, LLC

发明人： Kenneth Colin Dyer

IPC分类号： H03M1/06 ,  G06K9/62 ,  G06N3/04 ,  H03M1/10

CPC分类号： H03M1/0687 ,  G06K9/6256 ,  G06N3/04 ,  H03M1/1052

摘要： Embodiments of the present disclosure includes systems and methods for diagnosing and correcting deficiencies in operation of integrated circuits. A set of operational data of an integrated circuit is received by a network via a communication interface. A deficiency in operation of the integrated circuit is diagnosed based on the set of operational data. A correction is generated for improving operation of the integrated circuit based on the deficiency diagnosed. The correction is transmitted over the network via the communication interface to the integrated circuit.

公开(公告)号：US20140082451A1

公开(公告)日：2014-03-20

申请号：US14083059

申请日：2013-11-18

申请人： Sivakumar Radhakrishnan ,  Mark A. Schmisseur ,  Sin S. Tan ,  Kenneth C. Haren ,  Thomas C. Brown ,  Pankaj Kumar ,  Vinodh Gopal ,  Wajdi K. Feghali

发明人： Sivakumar Radhakrishnan ,  Mark A. Schmisseur ,  Sin S. Tan ,  Kenneth C. Haren ,  Thomas C. Brown ,  Pankaj Kumar ,  Vinodh Gopal ,  Wajdi K. Feghali

IPC分类号： G06F11/10

CPC分类号： G06F11/10 ,  G06F11/1076 ,  H03M1/1052 ,  H03M7/42 ,  H03M13/09 ,  H03M13/091 ,  H03M13/158 ,  H03M13/6575

摘要： Embodiments of the present disclosure describe methods, apparatus, and system configurations for cyclic redundancy check circuits using Galois-field arithmetic.

摘要翻译： 本公开的实施例描述了使用伽罗瓦域算术的循环冗余校验电路的方法，装置和系统配置。

公开(公告)号：US08154432B2

公开(公告)日：2012-04-10

申请号：US12728749

申请日：2010-03-22

申请人： Valery S. Kaper ,  John P. Bettencourt

发明人： Valery S. Kaper ,  John P. Bettencourt

IPC分类号： H03M1/10

CPC分类号： H03M1/1052 ,  H03M1/66

摘要： A system having: a digital pre-distortion circuit fed by a digital signal for distorting the digital signal; a digital to analog converter (DAC) core section coupled to an output of the calibration circuit for converting the distorted digital signal into a corresponding analog signal, the DAC core section performing the conversion in accordance with a control signal fed to the DAC core section; a power amplifier (PA) section coupled to an output of the DAC core section for amplifying power in the analog signal; and a calibration circuit coupled to the output of the power amplifier for producing, in response to the power in the power amplified analog signal, the control signal for the DAC core section.

摘要翻译： 一种具有：数字预失真电路的数字预失真电路，由数字信号馈送以扭曲数字信号; 耦合到所述校准电路的输出的数模转换器（DAC）核心部分，用于将失真的数字信号转换成对应的模拟信号，所述DAC核部分根据馈送到所述DAC核心部分的控制信号执行转换; 功率放大器（PA）部分，耦合到DAC核心部分的输出端，用于放大模拟信号的功率; 以及耦合到所述功率放大器的输出的校准电路，用于响应于功率放大模拟信号中的功率而产生用于DAC核心部分的控制信号。

公开(公告)号：US20110227770A1

公开(公告)日：2011-09-22

申请号：US12728749

申请日：2010-03-22

申请人： Valery S. Kaper ,  John P. Bettencourt

发明人： Valery S. Kaper ,  John P. Bettencourt

IPC分类号： H03M1/66 ,  H03M1/10

CPC分类号： H03M1/1052 ,  H03M1/66

摘要： A system having: a digital pre-distortion circuit fed by a digital signal for distorting the digital signal; a digital to analog converter (DAC) core section coupled to an output of the calibration circuit for converting the distorted digital signal into a corresponding analog signal, the DAC core section performing the conversion in accordance with a control signal fed to the DAC core section; a power amplifier (PA) section coupled to an output of the DAC core section for amplifying power in the analog signal; and a calibration circuit coupled to the output of the power amplifier for producing, in response to the power in the power amplified analog signal, the control signal for the DAC core section.

摘要翻译： 一种具有：数字预失真电路的数字预失真电路，由数字信号馈送以扭曲数字信号; 耦合到所述校准电路的输出的数模转换器（DAC）核心部分，用于将失真的数字信号转换成对应的模拟信号，所述DAC核部分根据馈送到所述DAC核心部分的控制信号执行转换; 功率放大器（PA）部分，耦合到DAC核心部分的输出端，用于放大模拟信号的功率; 以及耦合到所述功率放大器的输出的校准电路，用于响应于功率放大模拟信号中的功率而产生用于DAC核心部分的控制信号。

公开(公告)号：US20100314560A1

公开(公告)日：2010-12-16

申请号：US12800568

申请日：2010-05-18

申请人： Hidefumi Yabara

发明人： Hidefumi Yabara

IPC分类号： G21K5/00 ,  H03M1/06

CPC分类号： H03M1/1052 ,  H03M1/687

摘要： A D/A converter includes a D/A converter base part having a first D/A converter unit performing D/A conversion of high order bits and a second D/A converter unit performing D/A conversion of low order bits and including an auxiliary bit assigned an identical weight to a least significant bit, a correction D/A converter part, an error detection processing section generating a digital code to be set to a correction D/A converter unit in the correction D/A converter part, and a control section. The control section compares one bit current source with another bit current source in a lower order than the one bit current source, and corrects a value of the one bit current source by causing the error detection processing section to generate the digital code to be set to the correction D/A converter unit when judging that the value of the one bit current source changes.

摘要翻译： AD / A转换器包括具有执行高阶比特D / A转换的第一D / A转换器单元的D / A转换器基座部分和执行低位比特的D / A转换的第二D / A转换器单元，并且包括辅助 比特分配与最低有效位相同的权重，校正D / A转换器部分，产生将被设置到校正D / A转换器部分中的校正D / A转换器单元的数字代码的错误检测处理部分，以及 控制部分。 控制部分将一位电流源与另一位电流源以比一位电流源更低的顺序进行比较，并通过使错误检测处理部分生成要设置为的数字代码来校正一位电流源的值 校正D / A转换器单元当判断一位电流源的值改变时。

公开(公告)号：US07425908B2

公开(公告)日：2008-09-16

申请号：US10581549

申请日：2004-11-30

申请人： Patrick Gremillet

发明人： Patrick Gremillet

IPC分类号： H03M1/10

CPC分类号： H03M1/1052 ,  H03M1/1085 ,  H03M1/1215

摘要： A method for generating a digital signal representative of the pairing error between the channels of an analog digital conversion system with time interleaving, and a method for suppressing the errors thus calculated and an analog digital conversion system with time interleaving using same. The method comprises determining a spectrum (11-12) of the digital signal as a function of a frequency response of the analog digital conversion system with time interleaving (CAN 10) to at least one analog calibration signal (IC), and generating a “comb” signal whose spectrum is composed of frequency lines kFs/N, where Fs is a sampling frequency and N a number of channels of the analog digital conversion system with time interleaving, and whose amplitude is dependent on the frequency response of the analog digital converter.

摘要翻译： 一种用于产生代表模拟数字转换系统的信道与时间交织之间的配对误差的数字信号的方法以及用于抑制如此计算的误差的方法和使用其的时间交织的模拟数字转换系统。 该方法包括根据随时间交织（CAN 10）至少一个模拟校准信号（IC）的模拟数字转换系统的频率响应来确定数字信号的频谱（11-12），并产生“ 梳状“信号，其频谱由频率线kFs / N组成，其中Fs是采样频率，N是具有时间交织的模拟数字转换系统的通道数，并且其幅度取决于模拟数字转换器的频率响应 。

公开(公告)号：US06720896B2

公开(公告)日：2004-04-13

申请号：US10067173

申请日：2002-02-04

申请人： Joseph Semmler ,  Frank Lehmacher

发明人： Joseph Semmler ,  Frank Lehmacher

IPC分类号： H03M110

CPC分类号： H03M1/1052 ,  H03M1/0619 ,  H03M1/1023 ,  H03M1/468 ,  H03M1/804

摘要： An A/D converter or D/A converter has an internal voltage selection device. Several reference voltages are available for selection by the selection device, which selects a voltage based on a selection signal and feeds the reference voltage to a conversion device of the converter. A correction network is provided for correcting offset and linearity errors. The plurality of reference voltages are freely selectable reference voltages, and the specific reference voltage defining the conversion is freely selectable, that is, it is freely selectable what reference voltage is used to carry out a respective conversion.

摘要翻译： A / D转换器或D / A转换器具有内部电压选择装置。 多个参考电压可供选择装置选择，选择装置根据选择信号选择电压，并将参考电压馈送到转换器的转换装置。 提供校正网络用于校正偏移和线性误差。 多个参考电压是可自由选择的参考电压，并且限定转换的特定参考电压是可自由选择的，即，可以自由地选择使用什么参考电压来执行相应的转换。

公开(公告)号：US20020126033A1

公开(公告)日：2002-09-12

申请号：US10067173

申请日：2002-02-04

发明人： Joseph Semmler ,  Frank Lehmacher

IPC分类号： H03M001/34

CPC分类号： H03M1/1052 ,  H03M1/0619 ,  H03M1/1023 ,  H03M1/468 ,  H03M1/804

摘要： An A/D converter or D/A converter has an internal voltage selection device. Several reference voltages are available for selection by the selection device, which selects a voltage based on a selection signal and feeds the reference voltage to a conversion device of the converter. A correction network is provided for correcting offset and linearity errors. The plurality of reference voltages are freely selectable reference voltages, and the specific reference voltage defining the conversion is freely selectable, that is, it is freely selectable what reference voltage is used to carry out a respective conversion.

摘要翻译： A / D转换器或D / A转换器具有内部电压选择装置。 多个参考电压可供选择装置选择，选择装置根据选择信号选择电压，并将参考电压馈送到转换器的转换装置。 提供校正网络用于校正偏移和线性误差。 多个参考电压是可自由选择的参考电压，并且限定转换的特定参考电压是可自由选择的，即，可以自由地选择使用什么参考电压来执行相应的转换。

公开(公告)号：US09141469B2

公开(公告)日：2015-09-22

申请号：US14083059

申请日：2013-11-18

申请人： Intel Corporation

发明人： Sivakumar Radhakrishnan ,  Mark A. Schmisseur ,  Sin S. Tan ,  Kenneth C. Haren ,  Thomas C. Brown ,  Pankaj Kumar ,  Vinodh Gopal ,  Wajdi K. Feghali

IPC分类号： G06F11/10 ,  H03M13/00 ,  H03M1/10 ,  H03M7/42 ,  H03M13/09 ,  H03M13/15

CPC分类号： G06F11/10 ,  G06F11/1076 ,  H03M1/1052 ,  H03M7/42 ,  H03M13/09 ,  H03M13/091 ,  H03M13/158 ,  H03M13/6575

摘要： Embodiments of the present disclosure describe methods, apparatus, and system configurations for cyclic redundancy check circuits using Galois-field arithmetic.

摘要翻译： 本公开的实施例描述了使用伽罗瓦域算术的循环冗余校验电路的方法，装置和系统配置。

公开(公告)号：US20140002284A1

公开(公告)日：2014-01-02

申请号：US13553017

申请日：2012-07-19

申请人： Loke TAN ,  Steven Jaffe ,  Hong Liu ,  Lin He ,  Randall Perlow ,  Peter Cangiane ,  Ramon Gomez ,  Giuseppe Cusmai

发明人： Loke TAN ,  Steven Jaffe ,  Hong Liu ,  Lin He ,  Randall Perlow ,  Peter Cangiane ,  Ramon Gomez ,  Giuseppe Cusmai

IPC分类号： H03M1/06

CPC分类号： H03M1/1052 ,  H03M1/1215

摘要： Various multi-lane ADCs are disclosed that substantially compensate for impairments present within various signals that result from various impairments, such as phase offset, amplitude offset, and/or DC offset to provide some examples, such that their respective digital output samples accurately represent their respective analog inputs. Generally, the various multi-lane ADCs determine various statistical relationships, such as various correlations to provide an example, between these various signals and various known calibration signals to quantify the phase offset, amplitude offset, and/or DC offset that may be present within the various signals. The various multi-lane ADCs adjust the various signals to substantially compensate for the phase offset, amplitude offset, and/or DC offset based upon these various statistical relationships such that their respective digital output samples accurately represent their respective analog inputs.

摘要翻译： 公开了各种多通道ADC，其基本上补偿由各种损伤产生的各种信号中存在的损伤，例如相位偏移，幅度偏移和/或DC偏移，以提供一些示例，使得它们各自的数字输出样本准确地表示它们 各自的模拟输入。 通常，各种多通道ADC确定各种统计关系，例如各种相关性，以提供这些各种信号之间的示例，以及各种已知的校准信号，以量化可能存在的相位偏移，幅度偏移和/或DC偏移 各种信号。 各种多通道ADC基于这些各种统计关系调整各种信号以基本上补偿相位偏移，幅度偏移和/或DC偏移，使得它们各自的数字输出样本精确地表示它们各自的模拟输入。