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1.发明授权System and method to optimize multi-core microprocessor performance using voltage offsets 失效使用电压补偿优化多核微处理器性能的系统和方法公开(公告)号：US07721119B2
公开(公告)日：2010-05-18
申请号：US11466891
申请日：2006-08-24
申请人： Louis Bennie Capps, Jr. , Warren D. Dyckman , Joanne Ferris , Anand Haridass , James Douglas Jordan , Ronald Edward Newhart , Michael Richard Ouellette , Michael Jay Shapiro
发明人： Louis Bennie Capps, Jr. , Warren D. Dyckman , Joanne Ferris , Anand Haridass , James Douglas Jordan , Ronald Edward Newhart , Michael Richard Ouellette , Michael Jay Shapiro
IPC分类号： G06F1/00
CPC分类号： G06F1/26
摘要： A system and method to optimize multi-core microprocessor performance using voltage offsets is presented. A multi-core device tests each of its processor cores in order to identify each processor core's optimum supply voltage. In turn, the device configures voltage offset networks for each processor core based upon each processor core's identified optimum supply voltage. As a result, the offset voltages produced by the voltage offset networks are subtracted from the multi-core device's main voltage, which results in the voltage offset networks supplying optimum supply voltages to each processor core. The voltage offset networks may include fuses to generate a fixed voltage offset, or the voltage offset networks may include a control circuit to dynamically adjust voltage offsets during the multi-core device's operation.
摘要翻译： 提出了使用电压偏移来优化多核微处理器性能的系统和方法。 多核设备测试每个处理器内核，以便识别每个处理器内核的最佳电源电压。 反过来，该设备基于每个处理器核心的所识别的最佳电源电压来配置每个处理器核心的电压偏移网络。 结果，从多核设备的主电压中减去由电压偏移网络产生的偏移电压，这导致电压偏移网络向每个处理器核提供最佳电源电压。 电压偏移网络可以包括熔丝以产生固定的电压偏移，或者电压偏移网络可以包括在多核装置的操作期间动态地调节电压偏移的控制电路。
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2.发明授权Method and apparatus for controlling heat generation in a multi-core processor 有权用于控制多核处理器中的发热的方法和装置公开(公告)号：US07617403B2
公开(公告)日：2009-11-10
申请号：US11459988
申请日：2006-07-26
CPC分类号： G06F1/206
摘要： The disclosed methodology and apparatus may reduce heat generation in a multi-core processor. In one embodiment, a multi-core processor cycles selected processor cores off in a predetermined pattern across the processor die over time to reduce the average heat generation by the processor. The disclosed multi-core processor may reduce or avoid undesirable hot spots that impact processor life.
摘要翻译： 所公开的方法和装置可以减少多核处理器中的发热。 在一个实施例中，多核处理器随着时间跨越处理器管芯以预定模式关闭所选择的处理器核，以减少处理器的平均发热量。 所公开的多核处理器可以减少或避免影响处理器寿命的不期望的热点。
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3.发明申请Method and Apparatus for Controlling Heat Generation in a Multi-Core Processor 有权用于控制多核处理器中的发热的方法和装置公开(公告)号：US20080028236A1
公开(公告)日：2008-01-31
申请号：US11459988
申请日：2006-07-26
IPC分类号： G06F1/00
CPC分类号： G06F1/206
摘要： The disclosed methodology and apparatus may reduce heat generation in a multi-core processor. In one embodiment, a multi-core processor cycles selected processor cores off in a predetermined pattern across the processor die over time to reduce the average heat generation by the processor. The disclosed multi-core processor may reduce or avoid undesirable hot spots that impact processor life.
摘要翻译： 所公开的方法和装置可以减少多核处理器中的发热。 在一个实施例中，多核处理器随着时间跨越处理器管芯以预定模式关闭所选择的处理器核，以减少处理器的平均发热量。 所公开的多核处理器可以减少或避免影响处理器寿命的不期望的热点。
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4.发明授权Method and apparatus for monitoring and controlling heat generation in a multi-core processor 失效用于在多核处理器中监测和控制发热的方法和装置公开(公告)号：US07584369B2
公开(公告)日：2009-09-01
申请号：US11460014
申请日：2006-07-26
CPC分类号： G06F1/206
摘要： The disclosed methodology and apparatus may control heat generation in a multi-core processor. In one embodiment, each processor core includes a temperature sensor that reports temperature information to a processor controller. If a particular processor core exceeds a predetermined temperature, the processor core disables that processor core to allow it to cool. The processor core enables the previously disabled processor when the previously disabled processor core cools sufficiently to a normal operating temperature. The disclosed multi-core processor may avoid undesirable hot spots that impact processor life.
摘要翻译： 所公开的方法和装置可以控制多核处理器中的发热。 在一个实施例中，每个处理器核心包括将温度信息报告给处理器控制器的温度传感器。 如果特定处理器核心超过预定温度，则处理器内核禁用该处理器核心以使其冷却。 当先前禁用的处理器内核足够冷却至正常工作温度时，处理器内核可以启用先前禁用的处理器。 所公开的多核处理器可以避免影响处理器寿命的不期望的热点。
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5.发明申请System and Method to Optimize Multi-Core Microprocessor Performance Using Voltage Offsets 失效使用电压偏移优化多核微处理器性能的系统和方法公开(公告)号：US20080052542A1
公开(公告)日：2008-02-28
申请号：US11466891
申请日：2006-08-24
申请人： Louis Bennie Capps , Warren D. Dyckman , Joanne Ferris , Anand Haridass , James Douglas Jordan , Ronald Edward Newhart , Michael Richard Ouellette , Michael Jay Shapiro
发明人： Louis Bennie Capps , Warren D. Dyckman , Joanne Ferris , Anand Haridass , James Douglas Jordan , Ronald Edward Newhart , Michael Richard Ouellette , Michael Jay Shapiro
IPC分类号： G06F1/00
CPC分类号： G06F1/26
摘要： A system and method to optimize multi-core microprocessor performance using voltage offsets is presented. A multi-core device tests each of its processor cores in order to identify each processor core's optimum supply voltage. In turn, the device configures voltage offset networks for each processor core based upon each processor core's identified optimum supply voltage. As a result, the offset voltages produced by the voltage offset networks are subtracted from the multi-core device's main voltage, which results in the voltage offset networks supplying optimum supply voltages to each processor core. The voltage offset networks may include fuses to generate a fixed voltage offset, or the voltage offset networks may include a control circuit to dynamically adjust voltage offsets during the multi-core device's operation.
摘要翻译： 提出了使用电压偏移来优化多核微处理器性能的系统和方法。 多核设备测试每个处理器内核，以便识别每个处理器内核的最佳电源电压。 反过来，该设备基于每个处理器核心的所识别的最佳电源电压来配置每个处理器核心的电压偏移网络。 结果，从多核设备的主电压中减去由电压偏移网络产生的偏移电压，这导致电压偏移网络向每个处理器核提供最佳电源电压。 电压偏移网络可以包括熔丝以产生固定的电压偏移，或者电压偏移网络可以包括在多核装置的操作期间动态地调节电压偏移的控制电路。
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6.发明授权Structure for an apparatus for monitoring and controlling heat generation in a multi-core processor 有权用于在多核处理器中监测和控制发热的装置的结构公开(公告)号：US08214660B2
公开(公告)日：2012-07-03
申请号：US12347947
申请日：2008-12-31
CPC分类号： G06F1/206
摘要： A design structure for a processor may be embodied in a machine readable medium for designing, manufacturing or testing a processor integrated circuit. The design structure may control heat generation in a multi-core processor. The design structure may specify that each processor core includes a temperature sensor that reports temperature information to a processor controller. The design structure may also specify that if a particular processor core exceeds a predetermined temperature, the processor controller disables that processor core to allow that processor core to cool. The design structure may also specify that the processor controller enables the previously disabled processor core when the previously disabled processor core cools sufficiently to a normal operating temperature. In this manner, a multi-core processor may avoid undesirable hot spots that impact processor life.
摘要翻译： 用于处理器的设计结构可以体现在用于设计，制造或测试处理器集成电路的机器可读介质中。 该设计结构可以控制多核处理器中的发热。 设计结构可以指定每个处理器核心包括向处理器控制器报告温度信息的温度传感器。 该设计结构还可以指定如果特定处理器核心超过预定温度，则处理器控制器禁止该处理器核心使该处理器核心冷却。 设计结构还可以指定当先前禁用的处理器核心充分冷却至正常工作温度时，处理器控制器启用先前禁用的处理器核心。 以这种方式，多核处理器可以避免影响处理器寿命的不期望的热点。
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7.发明申请Method and Apparatus for Monitoring and Controlling Heat Generation in a Multi-Core Processor 失效用于监控和控制多核处理器中发热的方法和装置公开(公告)号：US20080028244A1
公开(公告)日：2008-01-31
申请号：US11460014
申请日：2006-07-26
IPC分类号： G06F1/00
CPC分类号： G06F1/206
摘要： The disclosed methodology and apparatus may control heat generation in a multi-core processor. In one embodiment, each processor core includes a temperature sensor that reports temperature information to a processor controller. If a particular processor core exceeds a predetermined temperature, the processor core disables that processor core to allow it to cool. The processor core enables the previously disabled processor when the previously disabled processor core cools sufficiently to a normal operating temperature. The disclosed multi-core processor may avoid undesirable hot spots that impact processor life.
摘要翻译： 所公开的方法和装置可以控制多核处理器中的发热。 在一个实施例中，每个处理器核心包括将温度信息报告给处理器控制器的温度传感器。 如果特定处理器核心超过预定温度，则处理器内核禁用该处理器核心以使其冷却。 当先前禁用的处理器内核足够冷却至正常工作温度时，处理器内核可以启用先前禁用的处理器。 所公开的多核处理器可以避免影响处理器寿命的不期望的热点。
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8.发明授权Multicore processor and method of use that adapts core functions based on workload execution 有权基于工作负载执行的多核处理器和使用方法可以调整核心功能公开(公告)号：US08327126B2
公开(公告)日：2012-12-04
申请号：US12197357
申请日：2008-08-25
申请人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Thomas Edward Cook , Glenn G. Daves , Ronald Edward Newhart , Michael A. Paolini , Michael Jay Shapiro
发明人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Thomas Edward Cook , Glenn G. Daves , Ronald Edward Newhart , Michael A. Paolini , Michael Jay Shapiro
CPC分类号： G06F15/7871
摘要： A processor has multiple cores with each core having an associated function to support processor operations. The functions performed by the cores are selectively altered to improve processor operations by balancing the resources applied for each function. For example, each core comprises a field programmable array that is selectively and dynamically programmed to perform a function, such as a floating point function or a fixed point function, based on the number of operations that use each function. As another example, a processor is built with a greater number of cores than can be simultaneously powered, each core associated with a function, so that cores having functions with lower utilization are selectively powered down.
摘要翻译： 处理器具有多个核心，每个核心具有相关功能以支持处理器操作。 通过平衡应用于每个功能的资源，选择性地改变由核执行的功能以改善处理器操作。 例如，每个核心包括一个现场可编程阵列，该阵列可以根据使用每个功能的操作次数，选择性地和动态地编程来执行诸如浮点函数或固定点功能的功能。 作为另一示例，处理器被构建为具有比可以同时供电的更多数量的核，每个核与功能相关联，使得具有较低利用率的功能的核被选择性地关机。
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9.发明授权Optimizing execution of single-threaded programs on a multiprocessor managed by compilation 有权在编译器管理的多处理器上优化单线程程序的执行公开(公告)号：US08312455B2
公开(公告)日：2012-11-13
申请号：US11960021
申请日：2007-12-19
IPC分类号： G06F9/46
CPC分类号： G06F9/4843 , G06F9/3851
摘要： A method for optimizing execution of a single threaded program on a multi-core processor. The method includes dividing the single threaded program into a plurality of discretely executable components while compiling the single threaded program; identifying at least some of the plurality of discretely executable components for execution by an idle core within the multi-core processor; and enabling execution of the at least one of the plurality of discretely executable components on the idle core.
摘要翻译： 一种用于优化多核处理器上单个线程程序的执行的方法。 该方法包括在编译单线程程序时将单线程程序划分成多个可离散执行的组件; 识别所述多个离散可执行部件中的至少一些，以供所述多核处理器内的空闲核心执行; 以及允许在所述空闲核心上执行所述多个离散可执行组件中的至少一个。
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10.发明申请Optimizing Execution of Single-Threaded Programs on a Multiprocessor Managed by Compilation 有权通过编译管理的多处理器上优化单线程程序的执行公开(公告)号：US20090164755A1
公开(公告)日：2009-06-25
申请号：US11960021
申请日：2007-12-19
IPC分类号： G06F9/312
CPC分类号： G06F9/4843 , G06F9/3851
摘要： A method for optimizing execution of a single threaded program on a multi-core processor. The method includes dividing the single threaded program into a plurality of discretely executable components while compiling the single threaded program; identifying at least some of the plurality of discretely executable components for execution by an idle core within the multi-core processor; and enabling execution of the at least one of the plurality of discretely executable components on the idle core.
摘要翻译： 一种用于优化多核处理器上单个线程程序的执行的方法。 该方法包括在编译单线程程序时将单线程程序划分成多个可离散执行的组件; 识别所述多个离散可执行部件中的至少一些，以由所述多核处理器内的空闲核心执行; 以及允许在所述空闲核心上执行所述多个离散可执行组件中的至少一个。
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