公开(公告)号：US20110254121A1

公开(公告)日：2011-10-20

申请号：US12761780

申请日：2010-04-16

Applicant: Kangguo Cheng ,  Louis L. Hsu ,  William R. Tonti ,  Chih-Chao Yang

Inventor： Kangguo Cheng ,  Louis L. Hsu ,  William R. Tonti ,  Chih-Chao Yang

IPC: H01L23/525 ,  H01L21/768 ,  G06F17/50

CPC classification number: H01L23/5252 ,  G06F17/505 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Voltage programmable anti-fuse structures and methods are provided that include at least one conductive material island atop a dielectric surface that is located between two adjacent conductive features. In one embodiment, the anti-fuse structure includes a dielectric material having at least two adjacent conductive features embedded therein. At least one conductive material island is located on an upper surface of the dielectric material that is located between the at least two adjacent conductive features. A dielectric capping layer is located on exposed surfaces of the dielectric material, the at least one conductive material island and the at least two adjacent conductive features. When the anti-fuse structure is in a programmed state, a dielectric breakdown path is present in the dielectric material that is located beneath the at least one conductive material island which conducts electrical current to electrically couple the two adjacent conductive features.

Abstract translation: 提供了电压可编程的抗熔丝结构和方法，其包括位于介于两个相邻导电特征之间的电介质表面上的至少一个导电材料岛。 在一个实施例中，反熔丝结构包括具有嵌入其中的至少两个相邻导电特征的电介质材料。 至少一个导电材料岛位于介电材料的位于至少两个相邻导电特征之间的上表面上。 电介质覆盖层位于电介质材料的暴露表面上，至少一个导电材料岛和至少两个相邻的导电特征。 当反熔丝结构处于编程状态时，介电击穿路径存在于介电材料中，介电材料位于至少一个导电材料岛之下，该导电材料岛传导电流以电耦合两个相邻导电特征。

公开(公告)号：US20090280636A1

公开(公告)日：2009-11-12

申请号：US12118161

申请日：2008-05-09

Applicant: Louis L. Hsu ,  William R. Tonti ,  Chih-Chao Yang

Inventor： Louis L. Hsu ,  William R. Tonti ,  Chih-Chao Yang

IPC: H01L21/4763

CPC classification number: H01L21/76834 ,  H01L21/76807 ,  H01L21/76825 ,  H01L21/76849 ,  H01L23/5256 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods are provided for fabricating interconnect structures containing various capping materials for electrical fuses and other related applications. The method includes forming a first interconnect structure having a first interfacial structure and forming a second interconnect structure adjacent to the first structure. The second interconnect structure is formed with a second interfacial structure different from the first interfacial structure of the first interconnect structure.

Abstract translation: 提供了用于制造包含用于电熔丝和其它相关应用的各种封盖材料的互连结构的方法。 该方法包括形成具有第一界面结构并形成与第一结构相邻的第二互连结构的第一互连结构。 第二互连结构形成有与第一互连结构的第一界面结构不同的第二界面结构。

公开(公告)号：US08232649B2

公开(公告)日：2012-07-31

申请号：US13052662

申请日：2011-03-21

Applicant: Louis L. Hsu ,  William R. Tonti ,  Chih-Chao Yang

Inventor： Louis L. Hsu ,  William R. Tonti ,  Chih-Chao Yang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/58 ,  H01L23/62 ,  H01L29/00 ,  H01L27/10 ,  H01L29/73 ,  H01L29/74

CPC classification number: H01L23/5256 ,  H01L21/76829 ,  H01L21/76838 ,  H01L21/76849 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different from the first interfacial structure.

Abstract translation: 为包含用于电熔丝和其它相关应用的各种封盖材料的互连结构提供了一种设计结构。 该结构包括具有第一界面结构的第一互连结构和与第一结构相邻的第二互连结构。 第二互连结构具有与第一界面结构不同的第二界面结构。

公开(公告)号：US08772156B2

公开(公告)日：2014-07-08

申请号：US12118161

申请日：2008-05-09

Applicant: Louis L. Hsu ,  William R. Tonti ,  Chih-Chao Yang

Inventor： Louis L. Hsu ,  William R. Tonti ,  Chih-Chao Yang

IPC: H01L21/4763

CPC classification number: H01L21/76834 ,  H01L21/76807 ,  H01L21/76825 ,  H01L21/76849 ,  H01L23/5256 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods are provided for fabricating interconnect structures containing various capping materials for electrical fuses and other related applications. The method includes forming a first interconnect structure having a first interfacial structure and forming a second interconnect structure adjacent to the first structure. The second interconnect structure is formed with a second interfacial structure different from the first interfacial structure of the first interconnect structure.

Abstract translation: 提供了用于制造包含用于电熔丝和其它相关应用的各种封盖材料的互连结构的方法。 该方法包括形成具有第一界面结构并形成与第一结构相邻的第二互连结构的第一互连结构。 第二互连结构形成有与第一互连结构的第一界面结构不同的第二界面结构。

公开(公告)号：US08558384B2

公开(公告)日：2013-10-15

申请号：US13537879

申请日：2012-06-29

Applicant: Louis L. Hsu ,  William R. Tonti ,  Chih-Chao Yang

Inventor： Louis L. Hsu ,  William R. Tonti ,  Chih-Chao Yang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/5256 ,  H01L21/76829 ,  H01L21/76838 ,  H01L21/76849 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different from the first interfacial structure.

Abstract translation: 为包含用于电熔丝和其它相关应用的各种封盖材料的互连结构提供了一种设计结构。 该结构包括具有第一界面结构的第一互连结构和与第一结构相邻的第二互连结构。 第二互连结构具有与第一界面结构不同的第二界面结构。

公开(公告)号：US07956466B2

公开(公告)日：2011-06-07

申请号：US12118186

申请日：2008-05-09

Applicant: Louis L. Hsu ,  William R. Tonti ,  Chih-Chao Yang

Inventor： Louis L. Hsu ,  William R. Tonti ,  Chih-Chao Yang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L27/10 ,  H01L29/73 ,  H01L29/74

CPC classification number: H01L23/5256 ,  H01L21/76829 ,  H01L21/76838 ,  H01L21/76849 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different from the first interfacial structure.

Abstract translation: 为包含用于电熔丝和其它相关应用的各种封盖材料的互连结构提供了一种设计结构。 该结构包括具有第一界面结构的第一互连结构和与第一结构相邻的第二互连结构。 第二互连结构具有与第一界面结构不同的第二界面结构。

公开(公告)号：US20090278228A1

公开(公告)日：2009-11-12

申请号：US12118186

申请日：2008-05-09

Applicant: Louis L. Hsu ,  William R. Tonti ,  Chih-Chao Yang

Inventor： Louis L. Hsu ,  William R. Tonti ,  Chih-Chao Yang

IPC: H01L23/525

CPC classification number: H01L23/5256 ,  H01L21/76829 ,  H01L21/76838 ,  H01L21/76849 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different from the first interfacial structure.

Abstract translation: 为包含用于电熔丝和其它相关应用的各种封盖材料的互连结构提供了一种设计结构。 该结构包括具有第一界面结构的第一互连结构和与第一结构相邻的第二互连结构。 第二互连结构具有与第一界面结构不同的第二界面结构。

公开(公告)号：US08471356B2

公开(公告)日：2013-06-25

申请号：US12761780

申请日：2010-04-16

Applicant: Kangguo Cheng ,  Louis L. Hsu ,  William R. Tonti ,  Chih-Chao Yang

Inventor： Kangguo Cheng ,  Louis L. Hsu ,  William R. Tonti ,  Chih-Chao Yang

IPC: G06F17/50 ,  H01L21/768 ,  H01L23/525

CPC classification number: H01L23/5252 ,  G06F17/505 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Voltage programmable anti-fuse structures and methods are provided that include at least one conductive material island atop a dielectric surface that is located between two adjacent conductive features. In one embodiment, the anti-fuse structure includes a dielectric material having at least two adjacent conductive features embedded therein. At least one conductive material island is located on an upper surface of the dielectric material that is located between the at least two adjacent conductive features. A dielectric capping layer is located on exposed surfaces of the dielectric material, the at least one conductive material island and the at least two adjacent conductive features. When the anti-fuse structure is in a programmed state, a dielectric breakdown path is present in the dielectric material that is located beneath the at least one conductive material island which conducts electrical current to electrically couple the two adjacent conductive features.

Abstract translation: 提供了电压可编程的抗熔丝结构和方法，其包括位于介于两个相邻导电特征之间的电介质表面上的至少一个导电材料岛。 在一个实施例中，反熔丝结构包括具有嵌入其中的至少两个相邻导电特征的电介质材料。 至少一个导电材料岛位于介电材料的位于至少两个相邻导电特征之间的上表面上。 电介质覆盖层位于电介质材料的暴露表面上，至少一个导电材料岛和至少两个相邻的导电特征。 当反熔丝结构处于编程状态时，介电击穿路径存在于介电材料中，介电材料位于至少一个导电材料岛之下，该导电材料岛传导电流以电耦合两个相邻导电特征。

公开(公告)号：US07381594B2

公开(公告)日：2008-06-03

申请号：US11290890

申请日：2005-11-30

Applicant: Louis L. Hsu ,  Jack A. Mandelman ,  William R. Tonti ,  Chih-Chao Yang

Inventor： Louis L. Hsu ,  Jack A. Mandelman ,  William R. Tonti ,  Chih-Chao Yang

IPC: H01L21/82 ,  H01L21/8238 ,  H01L21/336 ,  H01L21/331

CPC classification number: H01L23/5256 ,  H01L21/268 ,  H01L21/84 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure including at least one e-fuse embedded within a trench that is located in a semiconductor substrate (bulk or semiconductor-on-insulator) is provided. In accordance with the present invention, the e-fuse is in electrical contact with a dopant region that is located within the semiconductor substrate. The present invention also provides a method of fabricating such a semiconductor structure in which the embedded e-fuse is formed substantially at the same time with the trench isolation regions.

Abstract translation: 提供了包括位于半导体衬底（主体或绝缘体中半导体）的沟槽内的至少一个电子熔丝的半导体结构。 根据本发明，电熔丝与位于半导体衬底内的掺杂区电接触。 本发明还提供一种制造这种半导体结构的方法，其中嵌入式电熔丝基本上与沟槽隔离区域同时形成。

公开(公告)号：US20120188002A1

公开(公告)日：2012-07-26

申请号：US13438230

申请日：2012-04-03

Applicant: Louis L. Hsu ,  Xu Ouyang ,  Chih-Chao Yang

Inventor： Louis L. Hsu ,  Xu Ouyang ,  Chih-Chao Yang

IPC: H03K17/687 ,  H01L21/02

CPC classification number: H01L28/40 ,  H01L22/14 ,  H01L22/22 ,  H01L22/34 ,  H01L23/5223 ,  H01L27/0688 ,  H01L27/0805 ,  H01L28/60 ,  H01L2924/0002 ,  Y10T307/865 ,  H01L2924/00

Abstract: A modularized capacitor array includes a plurality of capacitor modules. Each capacitor module includes a capacitor and a switching device that is configured to electrically disconnect the capacitor. The switching device includes a sensing unit configured to detect the level of leakage of the capacitor so that the switching device disconnects the capacitor electrically if the leakage current exceeds a predetermined level. Each capacitor module can include a single capacitor plate, two capacitor plates, or more than two capacitor plates. The leakage sensors and switching devices are employed to electrically disconnect any capacitor module of the capacitor array that becomes leaky, thereby protecting the capacitor array from excessive electrical leakage.

Abstract translation: 模块化电容器阵列包括多个电容器模块。 每个电容器模块包括电容器和被配置为电气断开电容器的开关装置。 开关装置包括：感测单元，被配置为检测电容器的泄漏电平，使得如果泄漏电流超过预定电平，则开关装置电连接电容器。 每个电容器模块可以包括单个电容器板，两个电容器板或多于两个的电容器板。 泄漏传感器和开关装置用于电气断开任何电容器阵列的电容器模块，从而保护电容器阵列免于漏电。