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    Unified non-partitioned register files for a digital signal processor operating in an interleaved multi-threaded environment
    3.
    发明申请
    Unified non-partitioned register files for a digital signal processor operating in an interleaved multi-threaded environment 审中-公开
    用于在交错多线程环境中工作的数字信号处理器的统一非分区寄存器文件

    公开(公告)号：US20060230253A1

    公开(公告)日：2006-10-12

    申请号：US11103744

    申请日：2005-04-11

    申请人： Lucian Codrescu ,  Erich Plondke ,  Muhammad Ahmed ,  William Anderson ,  Taylor Simpson

    发明人： Lucian Codrescu ,  Erich Plondke ,  Muhammad Ahmed ,  William Anderson ,  Taylor Simpson

    IPC分类号： G06F15/00

    CPC分类号： H04M1/72522 ,  G06F9/3012 ,  G06F9/3885 ,  H04M1/2535 ,  H04M2250/02

    摘要： A processor device is disclosed and includes a memory and a sequencer that is responsive to the memory. The sequencer can support very long instruction word (VLIW) instructions and superscalar instructions. The processor device further includes a first instruction execution unit responsive to the sequencer, a second instruction execution unit responsive to the sequencer, a third instruction execution unit responsive to the sequencer, and a fourth instruction execution unit responsive to the sequencer. Further, the processor device includes a plurality of register files and each of the plurality of register files includes a plurality of registers. The plurality of register files are coupled to the sequencer and coupled to the first instruction execution unit, the second instruction execution unit, the third instruction execution unit, and the fourth instruction execution unit.

    摘要翻译： 公开了处理器设备，并且包括响应于存储器的存储器和定序器。 音序器可以支持非常长的指令字（VLIW）指令和超标量指令。 处理器装置还包括响应于定序器的第一指令执行单元，响应于定序器的第二指令执行单元，响应于定序器的第三指令执行单元，以及响应于定序器的第四指令执行单元。 此外，处理器装置包括多个寄存器文件，并且多个寄存器文件中的每一个包括多个寄存器。 多个寄存器文件耦合到定序器并耦合到第一指令执行单元，第二指令执行单元，第三指令执行单元和第四指令执行单元。

    System and method of processing data using scalar/vector instructions
    4.
    发明授权
    System and method of processing data using scalar/vector instructions 有权
    使用标量/向量指令处理数据的系统和方法

    公开(公告)号：US07676647B2

    公开(公告)日：2010-03-09

    申请号：US11506584

    申请日：2006-08-18

    申请人： Lucian Codrescu ,  Erich Plondke ,  Taylor Simpson

    发明人： Lucian Codrescu ,  Erich Plondke ,  Taylor Simpson

    IPC分类号： G06F15/00

    CPC分类号： G06F9/30101 ,  G06F9/30021 ,  G06F9/30094 ,  G06F9/3885

    摘要： A processor device is disclosed that includes a register file with a combined condition code register for scalar and vector operations. The processor device utilizes the combined condition code register for scalar and vector operations. Further, a compare operation can store resulting bits in the combined condition code register and a conditional operation can utilize the combined condition code register bits for evaluating a condition.

    摘要翻译： 公开了一种处理器装置，其包括具有用于标量和矢量操作的组合条件码寄存器的寄存器文件。 处理器设备利用组合条件码寄存器进行标量和矢量操作。 此外，比较操作可以将结果位存储在组合条件码寄存器中，并且条件操作可以利用组合条件码寄存器位来评估条件。

    System and method of processing data using scalar/vector instructions
    5.
    发明申请
    System and method of processing data using scalar/vector instructions 有权
    使用标量/向量指令处理数据的系统和方法

    公开(公告)号：US20080046683A1

    公开(公告)日：2008-02-21

    申请号：US11506584

    申请日：2006-08-18

    申请人： Lucian Codrescu ,  Erich Plondke ,  Taylor Simpson

    发明人： Lucian Codrescu ,  Erich Plondke ,  Taylor Simpson

    IPC分类号： G06F15/76

    CPC分类号： G06F9/30101 ,  G06F9/30021 ,  G06F9/30094 ,  G06F9/3885

    摘要： A processor device is disclosed that includes a register file with a combined condition code register for scalar and vector operations. The processor device utilizes the combined condition code register for scalar and vector operations. Further, a compare operation can store resulting bits in the combined condition code register and a conditional operation can utilize the combined condition code register bits for evaluating a condition.

    摘要翻译： 公开了一种处理器装置，其包括具有用于标量和矢量操作的组合条件码寄存器的寄存器文件。 处理器设备利用组合条件码寄存器进行标量和矢量操作。 此外，比较操作可以将结果位存储在组合条件码寄存器中，并且条件操作可以利用组合条件码寄存器位来评估条件。

    System and Method of Processing Data Using Scalar/Vector Instructions
    6.
    发明申请
    System and Method of Processing Data Using Scalar/Vector Instructions 有权
    使用标量/向量指令处理数据的系统和方法

    公开(公告)号：US20100118852A1

    公开(公告)日：2010-05-13

    申请号：US12690213

    申请日：2010-01-20

    申请人： Lucian Codrescu ,  Erich J. Plondke ,  Taylor Simpson

    发明人： Lucian Codrescu ,  Erich J. Plondke ,  Taylor Simpson

    IPC分类号： H04W4/00 ,  G06F9/30 ,  G06F9/312

    CPC分类号： G06F9/30101 ,  G06F9/30021 ,  G06F9/30094 ,  G06F9/3885

    摘要： A method of processing data is disclosed that includes performing a fetch of a plurality of instructions from a memory unit. The method also includes grouping the plurality of instructions into packets of instructions of different types for parallel execution by a plurality of instruction execution units. The packets of instructions include a first instruction and a second instruction. The method includes using a combined scalar and vector condition code register to execute the first instruction for a compare operation and the second instruction for a conditional operation using the combined scalar and vector condition code register. The method also includes when the compare operation is a scalar compare operation, receiving a scalar compare instruction for the scalar compare operation at an instruction executing unit and storing results of the scalar compare operation in the combined scalar and vector condition code register.

    摘要翻译： 公开了一种处理数据的方法，包括执行从存储器单元获取多个指令。 该方法还包括将多个指令分组为不同类型的指令包，以由多个指令执行单元并行执行。 指令包包括第一指令和第二指令。 该方法包括使用组合标量和向量条件码寄存器来执行用于比较操作的第一指令和使用组合标量和向量条件码寄存器的条件操作的第二指令。 该方法还包括当比较操作是标量比较操作时，在指令执行单元处接收用于标量比较操作的标量比较指令，并存储组合标量和向量条件代码寄存器中的标量比较操作的结果。

    System and method of processing data using scalar/vector instructions
    7.
    发明授权
    System and method of processing data using scalar/vector instructions 有权
    使用标量/向量指令处理数据的系统和方法

    公开(公告)号：US08190854B2

    公开(公告)日：2012-05-29

    申请号：US12690213

    申请日：2010-01-20

    申请人： Lucian Codrescu ,  Erich J. Plondke ,  Taylor Simpson

    发明人： Lucian Codrescu ,  Erich J. Plondke ,  Taylor Simpson

    IPC分类号： G06F9/00 ,  G06F9/305 ,  G06F15/80

    CPC分类号： G06F9/30101 ,  G06F9/30021 ,  G06F9/30094 ,  G06F9/3885

    摘要： A method of processing data is disclosed that includes performing a fetch of a plurality of instructions from a memory unit. The method also includes grouping the plurality of instructions into packets of instructions of different types for parallel execution by a plurality of instruction execution units. The packets of instructions include a first instruction and a second instruction. The method includes using a combined scalar and vector condition code register to execute the first instruction for a compare operation and the second instruction for a conditional operation using the combined scalar and vector condition code register. The method also includes when the compare operation is a scalar compare operation, receiving a scalar compare instruction for the scalar compare operation at an instruction executing unit and storing results of the scalar compare operation in the combined scalar and vector condition code register.

    摘要翻译： 公开了一种处理数据的方法，包括执行从存储器单元获取多个指令。 该方法还包括将多个指令分组为不同类型的指令包，以由多个指令执行单元并行执行。 指令包包括第一指令和第二指令。 该方法包括使用组合标量和向量条件码寄存器来执行用于比较操作的第一指令和使用组合标量和向量条件码寄存器的条件操作的第二指令。 该方法还包括当比较操作是标量比较操作时，在指令执行单元处接收用于标量比较操作的标量比较指令，并存储组合标量和向量条件代码寄存器中的标量比较操作的结果。