利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

36 条记录 (耗时 0.031 秒)

    Method and system for variable thread allocation and switching in a multithreaded processor
    2.
    发明授权
    Method and system for variable thread allocation and switching in a multithreaded processor 有权
    多线程处理器中可变线程分配和切换的方法和系统

    公开(公告)号：US07917907B2

    公开(公告)日：2011-03-29

    申请号：US11089474

    申请日：2005-03-23

    申请人： Muhammad Ahmed ,  Sujat Jamil ,  Erich Plondke ,  Lucian Codrescu ,  William C. Anderson

    发明人： Muhammad Ahmed ,  Sujat Jamil ,  Erich Plondke ,  Lucian Codrescu ,  William C. Anderson

    IPC分类号： G06F9/46 ,  G06F15/76

    CPC分类号： G06F9/3851

    摘要： Techniques for processing transmissions in a communications (e.g., CDMA) system. An aspect of the disclosed subject matter includes a method for processing instructions on a multithreaded processor. The multithreaded processor processes a plurality of threads via a plurality of processor pipelines. The method includes the step determining the operating frequency, F, at which the multithreaded processor operates. Then, the method determines a variable thread switch timeout state for triggering the switching of the processing among the plurality of active threads. The variable thread switch timeout state varies so that each of the plurality of active threads operates at a frequency of an allocated portion of the frequency, F. The allocated portion at which the active threads operate is determined at least in part in order to optimize the operation of the multithreaded processor. The method further switches the processing from a first one of the active threads to a next one of the active threads upon the occurrence of the variable thread switch timeout state.

    摘要翻译： 用于在通信（例如，CDMA）系统中处理传输的技术。 所公开的主题的一个方面包括用于在多线程处理器上处理指令的方法。 多线程处理器经由多个处理器管线处理多个线程。 该方法包括确定多线程处理器工作的工作频率F的步骤。 然后，该方法确定用于触发多个活动线程之间的处理切换的可变线程切换超时状态。 可变线程切换超时状态改变，使得多个活动线程中的每一个以所分配的频率部分F的频率运行。活动线程运行的分配部分至少部分地被确定，以便优化 操作多线程处理器。 在发生可变线程切换超时状态时，该方法还将处理从主动线程中的第一个切换到下一个活动线程。

    Method and system for variable thread allocation and switching in a multithreaded processor
    5.
    发明申请
    Method and system for variable thread allocation and switching in a multithreaded processor 有权
    多线程处理器中可变线程分配和切换的方法和系统

    公开(公告)号：US20060218559A1

    公开(公告)日：2006-09-28

    申请号：US11089474

    申请日：2005-03-23

    申请人： Muhammad Ahmed ,  Sujat Jamil ,  Erich Plondke ,  Lucian Codrescu ,  William Anderson

    发明人： Muhammad Ahmed ,  Sujat Jamil ,  Erich Plondke ,  Lucian Codrescu ,  William Anderson

    IPC分类号： G06F9/46

    CPC分类号： G06F9/3851

    摘要： Techniques for processing transmissions in a communications (e.g., CDMA) system. An aspect of the disclosed subject matter includes a method for processing instructions on a multithreaded processor. The multithreaded processor processes a plurality of threads via a plurality of processor pipelines. The method includes the step determining the operating frequency, F, at which the multithreaded processor operates. Then, the method determines a variable thread switch timeout state for triggering the switching of the processing among the plurality of active threads. The variable thread switch timeout state varies so that each of the plurality of active threads operates at a frequency of an allocated portion of the frequency, F. The allocated portion at which the active threads operate is determined at least in part in order to optimize the operation of the multithreaded processor. The method further switches the processing from a first one of the active threads to a next one of the active threads upon the occurrence of the variable thread switch timeout state.

    摘要翻译： 用于在通信（例如，CDMA）系统中处理传输的技术。 所公开的主题的一个方面包括用于在多线程处理器上处理指令的方法。 多线程处理器经由多个处理器管线处理多个线程。 该方法包括确定多线程处理器工作的工作频率F的步骤。 然后，该方法确定用于触发多个活动线程之间的处理切换的可变线程切换超时状态。 可变线程切换超时状态改变，使得多个活动线程中的每一个以所分配的频率部分F的频率运行。活动线程运行的分配部分至少部分地被确定，以便优化 操作多线程处理器。 在发生可变线程切换超时状态时，该方法还将处理从主动线程中的第一个切换到下一个活动线程。

    Variable interleaved multithreaded processor method and system
    7.
    发明申请
    Variable interleaved multithreaded processor method and system 审中-公开
    可变交错多线程处理器方法和系统

    公开(公告)号：US20060206902A1

    公开(公告)日：2006-09-14

    申请号：US11080239

    申请日：2005-03-14

    申请人： Sujat Jamil ,  Erich Plondke ,  Lucian Codrescu ,  Muhammad Ahmed ,  William Anderson

    发明人： Sujat Jamil ,  Erich Plondke ,  Lucian Codrescu ,  Muhammad Ahmed ,  William Anderson

    IPC分类号： G06F9/46

    CPC分类号： G06F9/3851

    摘要： Techniques for processing transmissions in a communications (e.g., CDMA) system. A multithreaded processor processes a plurality of threads operating via a plurality of processor pipelines associated with the multithreaded processor and predetermines a triggering event for the multithreaded processor to switch from a first thread to a second thread. The triggering event is variably and dynamically determined to optimize multithreaded processor performance. The triggering event may be a dynamically determined number of processor cycles, the number being determined to optimize the performance of the multithreaded processor, or a variably and dynamically determined event, such as a cache or instruction miss.

    摘要翻译： 用于在通信（例如，CDMA）系统中处理传输的技术。 多线程处理器处理通过与多线程处理器相关联的多个处理器管线操作的多个线程，并且预先确定用于多线程处理器从第一线程切换到第二线程的触发事件。 触发事件是可变和动态的，以优化多线程处理器性能。 触发事件可以是动态确定的处理器周期数，被确定为优化多线程处理器的性能的数量，或可变和动态确定的事件，例如高速缓存或指令未命中。

    Pointer computation method and system for a scalable, programmable circular buffer
    8.
    发明申请
    Pointer computation method and system for a scalable, programmable circular buffer 审中-公开
    指针计算方法和系统，用于可扩展的可编程循环缓冲区

    公开(公告)号：US20070094478A1

    公开(公告)日：2007-04-26

    申请号：US11255434

    申请日：2005-10-20

    申请人： Erich Plondke ,  Lucian Codrescu ,  Muhammad Ahmed ,  Mao Zeng ,  Sujat Jamil ,  William Anderson

    发明人： Erich Plondke ,  Lucian Codrescu ,  Muhammad Ahmed ,  Mao Zeng ,  Sujat Jamil ,  William Anderson

    IPC分类号： G06F12/00

    CPC分类号： G06F5/10 ,  G06F9/3552 ,  G06F9/3851 ,  G06F2205/106

    摘要： Techniques for processing digital signals for a variety of applications, including in a communications (e.g., CDMA) system. A pointer location within a circular buffer is determined by establishing a length of the circular buffer, a start address that is aligned to a power of 2, and an end address located distant from the start address by the length and less than a power of 2 greater than the length. The method and system determine a current pointer location for an address within the circular buffer, a stride value of bits between the start address and the end address, a new pointer location within the circular buffer that is shifted from the current pointer location by the number of bits of the stride value. An adjusted pointer location is within the circular buffer by an arithmetic operation of the new pointer location with the length.

    摘要翻译： 用于处理包括在通信（例如CDMA）系统中的各种应用的数字信号的技术。 循环缓冲器中的指针位置通过建立循环缓冲器的长度，与2的幂对齐的起始地址和远离起始地址长度并小于2的幂的结束地址来确定 大于长度。 该方法和系统确定循环缓冲器中的地址的当前指针位置，起始地址和结束地址之间的位的步幅值，循环缓冲器内的新指针位置，其从当前指针位置移位数字 的步幅值。 通过具有长度的新指针位置的算术运算，调整的指针位置在循环缓冲器内。

    Unified non-partitioned register files for a digital signal processor operating in an interleaved multi-threaded environment
    9.
    发明申请
    Unified non-partitioned register files for a digital signal processor operating in an interleaved multi-threaded environment 审中-公开
    用于在交错多线程环境中工作的数字信号处理器的统一非分区寄存器文件

    公开(公告)号：US20060230253A1

    公开(公告)日：2006-10-12

    申请号：US11103744

    申请日：2005-04-11

    申请人： Lucian Codrescu ,  Erich Plondke ,  Muhammad Ahmed ,  William Anderson ,  Taylor Simpson

    发明人： Lucian Codrescu ,  Erich Plondke ,  Muhammad Ahmed ,  William Anderson ,  Taylor Simpson

    IPC分类号： G06F15/00

    CPC分类号： H04M1/72522 ,  G06F9/3012 ,  G06F9/3885 ,  H04M1/2535 ,  H04M2250/02

    摘要： A processor device is disclosed and includes a memory and a sequencer that is responsive to the memory. The sequencer can support very long instruction word (VLIW) instructions and superscalar instructions. The processor device further includes a first instruction execution unit responsive to the sequencer, a second instruction execution unit responsive to the sequencer, a third instruction execution unit responsive to the sequencer, and a fourth instruction execution unit responsive to the sequencer. Further, the processor device includes a plurality of register files and each of the plurality of register files includes a plurality of registers. The plurality of register files are coupled to the sequencer and coupled to the first instruction execution unit, the second instruction execution unit, the third instruction execution unit, and the fourth instruction execution unit.

    摘要翻译： 公开了处理器设备，并且包括响应于存储器的存储器和定序器。 音序器可以支持非常长的指令字（VLIW）指令和超标量指令。 处理器装置还包括响应于定序器的第一指令执行单元，响应于定序器的第二指令执行单元，响应于定序器的第三指令执行单元，以及响应于定序器的第四指令执行单元。 此外，处理器装置包括多个寄存器文件，并且多个寄存器文件中的每一个包括多个寄存器。 多个寄存器文件耦合到定序器并耦合到第一指令执行单元，第二指令执行单元，第三指令执行单元和第四指令执行单元。

    Register files for a digital signal processor operating in an interleaved multi-threaded environment
    10.
    发明授权
    Register files for a digital signal processor operating in an interleaved multi-threaded environment 有权
    为交错多线程环境中的数字信号处理器注册文件

    公开(公告)号：US08713286B2

    公开(公告)日：2014-04-29

    申请号：US11115916

    申请日：2005-04-26

    申请人： Muhammad Ahmed ,  Erich Plondke ,  Lucian Codrescu ,  William C. Anderson

    发明人： Muhammad Ahmed ,  Erich Plondke ,  Lucian Codrescu ,  William C. Anderson

    IPC分类号： G06F7/57

    CPC分类号： G06F9/30149 ,  G06F9/3012 ,  G06F9/3851 ,  G06F9/3885

    摘要： A processor device is disclosed and includes a memory and a sequencer that is responsive to the memory. The sequencer supports very long instruction word (VLIW) type instructions and at least one VLIW instruction packet uses a number of operands during execution. The processor device further includes a plurality of instruction execution units responsive to the sequencer and a plurality of register files. Each of the plurality of register files includes a plurality of registers and the plurality of register files are coupled to the plurality of instruction execution units. Further, each of the plurality of register files includes a number of data read ports and the number of data read ports of each of the plurality of register files is less than the number of operands used by the at least one VLIW instruction packet.

    摘要翻译： 公开了处理器设备，并且包括响应于存储器的存储器和定序器。 定序器支持非常长的指令字（VLIW）类型指令，并且至少一个VLIW指令分组在执行期间使用多个操作数。 处理器设备还包括响应于定序器的多个指令执行单元和多个寄存器文件。 多个寄存器文件中的每一个包括多个寄存器，并且多个寄存器文件耦合到多个指令执行单元。 此外，多个寄存器文件中的每一个包括多个数据读取端口，并且多个寄存器堆栈中的每一个的数据读取端口的数量小于由至少一个VLIW指令包使用的操作数的数量。