公开(公告)号：US07046065B2

公开(公告)日：2006-05-16

申请号：US10684823

申请日：2003-10-14

Applicant: Ludovic Ruat ,  Dragos Davidescu

Inventor： Ludovic Ruat ,  Dragos Davidescu

IPC: G06F1/04

CPC classification number: G06F1/08

Abstract: A programmable clock generator delivers, using a primary clock signal of determined frequency, a first clock signal the frequency of which is equal to the frequency of the primary clock signal divided by a set point M. The set point M is a decimal number comprising a whole part M1 and a decimal part M2 and the clock generator modulates the period of the pulses of the first clock signal so that the duration of Ni successive pulses is substantially equal to M*Ni times the period of the primary clock signal, Ni being a reference number for modulating the period of the pulses of the first clock signal.

Abstract translation: 可编程时钟发生器使用确定频率的主时钟信号来传送其频率等于主时钟信号的频率除以设定点M的第一时钟信号。设定点M是十进制数，包括 整个部分M 1和小数部分M 2，并且时钟发生器调制第一时钟信号的脉冲的周期，使得Ni连续脉冲的持续时间基本上等于主时钟信号的周期的M * Ni，Ni 作为用于调制第一时钟信号的脉冲周期的参考号码。

公开(公告)号：US20050024111A1

公开(公告)日：2005-02-03

申请号：US10839978

申请日：2004-05-06

Applicant: Ludovic Ruat ,  Paul Kinowski ,  Alexander Czajor

Inventor： Ludovic Ruat ,  Paul Kinowski ,  Alexander Czajor

IPC: G06F1/12 ,  H03L7/00 ,  H04L7/04 ,  H03M1/00

CPC classification number: G06F1/12 ,  H03L7/00 ,  H04L7/044 ,  H04L7/046

Abstract: An integrated circuit having a clock calibration device receiving a local clock signal from an oscillator and applying a correction value to the signal to produce a corrected clock signal. The clock calibration device includes a frequency dividing module having a programmable divider and a calibration register for storing the correction value, the programmable divider receiving the local clock signal and delivering the corrected clock signal, and a circuit for determining a new correction value using an external reference signal. A time base unit produces a time base signal using a timing signal derived from the local clock signal, and it includes a counting module coupled to a load register wherein a load value is stored that determines the ratio between the frequency of the time base signal and that of the timing signal. An external computing unit loads a new load value into the load register by using the new correction value stored in the calibration register to deduce the new load value therefrom.

Abstract translation: 一种具有时钟校准装置的集成电路，其接收来自振荡器的本地时钟信号，并向该信号施加校正值以产生经校正的时钟信号。 时钟校准装置包括具有可编程分频器和用于存储校正值的校准寄存器的分频模块，可编程分频器接收本地时钟信号并传送校正后的时钟信号，以及用于使用外部电路确定新校正值的电路 参考信号。 时基单元使用从本地时钟信号导出的定时信号产生时基信号，并且其包括耦合到负载寄存器的计数模块，其中存储负载值，其确定时基信号的频率与时基信号的频率之间的比率 定时信号的。 外部计算单元通过使用存储在校准寄存器中的新校正值将新的负载值加载到装载寄存器中，从而推断出新的负载值。

公开(公告)号：US07408958B2

公开(公告)日：2008-08-05

申请号：US10826969

申请日：2004-03-31

Applicant: Ludovic Ruat ,  Paul Kinowski ,  Alexander Czajor

Inventor： Ludovic Ruat ,  Paul Kinowski ,  Alexander Czajor

IPC: H04J3/06

CPC classification number: G06F13/385

Abstract: An asynchronous data transmission device includes a data reception terminal receiving data clocked by a sampling signal in synchronization with a local clock signal. A register is connected to the data reception terminal for receiving the data. A clock deviation measuring circuit is connected to the register for determining a number M of periods of the sampling signal appearing during K periods of a synchronization signal received on the data reception terminal, and for comparing the number M to a tolerance margin defined by a lower threshold and an upper threshold.

Abstract translation: 异步数据传输装置包括数据接收终端，与本地时钟信号同步地接收由采样信号计时的数据。 寄存器连接到数据接收终端，用于接收数据。 时钟偏差测量电路连接到寄存器，用于确定在数据接收终端接收到的同步信号的K个周期期间出现的采样信号的周期数M，并将数M与由较低的 阈值和上限阈值。

公开(公告)号：US06913198B2

公开(公告)日：2005-07-05

申请号：US10873915

申请日：2004-06-22

Applicant: Ludovic Ruat ,  Olivier Ferrand ,  Bruno Gailhard

Inventor： Ludovic Ruat ,  Olivier Ferrand ,  Bruno Gailhard

IPC: G06K17/00 ,  G06K7/00 ,  G06K7/08 ,  G06K19/06

CPC classification number: G06K7/0069 ,  G06K7/0013 ,  G06K7/006 ,  G06K7/0086 ,  Y10T307/937

Abstract: A smart card reader includes a housing for receiving a smart card, a microprocessor, and a connector for connecting the microprocessor to the received smart card for establishing communications therebetween. A voltage source provides a power supply voltage to the microprocessor based upon the smart card being received in the housing. The smart card reader further includes a first switch interposed between the voltage source and a power supply terminal of the microprocessor. The first switch is closed when the received smart card is at an end of travel in the housing so that the power supply voltage is provided to the microprocessor, and is opened when the received smart card is no longer at the end of travel in the housing so that the power supply voltage is not provided to the microprocessor.

Abstract translation: 智能卡读取器包括用于接收智能卡的壳体，微处理器和用于将微处理器连接到接收的智能卡的连接器，用于在其间建立通信。 电压源基于智能卡被接收在外壳中而向微处理器提供电源电压。 智能卡读卡器还包括插入在电压源和微处理器的电源端之间的第一开关。 当接收到的智能卡处于壳体行程结束时，第一开关闭合，使得电源电压被提供给微处理器，并且当接收到的智能卡不再在外壳中行进结束时打开 使得不向微处理器提供电源电压。

公开(公告)号：US07502388B2

公开(公告)日：2009-03-10

申请号：US10824938

申请日：2004-04-15

Applicant: Ludovic Ruat ,  Paul Kinowski ,  Alexander Czajor

Inventor： Ludovic Ruat ,  Paul Kinowski ,  Alexander Czajor

IPC: H04J3/06

CPC classification number: G06F13/4081 ,  G06F13/385

Abstract: An asynchronous frame receiver includes an input for receiving an asynchronous frame comprising a break character, which includes a determined number of bits having a same value. A hot-plugging circuit for connecting to an asynchronous data bus that is operating by detecting the break character, and leaving an initial idle state and switching to at least one operating mode when the break character has been detected.

Abstract translation: 异步帧接收器包括用于接收包括断点字符的异步帧的输入，其包括具有相同值的确定数目的位。 一种热插拔电路，用于通过检测中断字符连接到正在运行的异步数据总线，并且当检测到断点字符时，保持初始空闲状态并切换到至少一个操作模式。

公开(公告)号：US06430250B1

公开(公告)日：2002-08-06

申请号：US09610506

申请日：2000-07-06

Applicant: Ludovic Ruat ,  Olivier Ferrand

Inventor： Ludovic Ruat ,  Olivier Ferrand

IPC: H03K2300

CPC classification number: G04F1/005

Abstract: The invention relates to a digital timer (20) comprising a binary counter (21) driven by a counting clock signal (Hc), the counter (21) presenting a stabilization time after each counting pulse, and means for delivering a detection signal (DS2) with a predetermined value when a counting order (N) is reached by the counter. According to the invention, the timer comprises wired logic means (22) arranged for detecting, at the output of the counter, a counting value (N−1) which is immediately before the counting order (N) in relation to the counting direction, and delivering an intermediate signal (DS1) with a predetermined value, as well means (24) for sampling the intermediate signal (DS1) at a moment when the counter receives the next counting pulse.

Abstract translation: 本发明涉及一种数字定时器（20），包括由计数时钟信号（Hc）驱动的二进制计数器（21），在每个计数脉冲之后呈现稳定时间的计数器（21）和用于传送检测信号（DS2 ）当计数器达到计数次序（N）时具有预定值。 根据本发明，定时器包括有线逻辑装置（22），布置成用于在计数器的输出处检测相对于计数方向紧接在计数指令（N）之前的计数值（N-1） 以及递送具有预定值的中间信号（DS1），以及用于在计数器接收到下一个计数脉冲的时刻对中间信号（DS1）进行采样的装置（24）。

公开(公告)号：US07078952B2

公开(公告)日：2006-07-18

申请号：US10839978

申请日：2004-05-06

Applicant: Ludovic Ruat ,  Paul Kinowski ,  Alexander Czajor

Inventor： Ludovic Ruat ,  Paul Kinowski ,  Alexander Czajor

IPC: G06F1/04 ,  H03K3/00

CPC classification number: G06F1/12 ,  H03L7/00 ,  H04L7/044 ,  H04L7/046

Abstract: An integrated circuit having a clock calibration device receiving a local clock signal from an oscillator and applying a correction value to the signal to produce a corrected clock signal. The clock calibration device includes a frequency dividing module having a programmable divider and a calibration register for storing the correction value, the programmable divider receiving the local clock signal and delivering the corrected clock signal, and a circuit for determining a new correction value using an external reference signal. A time base unit produces a time base signal using a timing signal derived from the local clock signal, and it includes a counting module coupled to a load register wherein a load value is stored that determines the ratio between the frequency of the time base signal and that of the timing signal. An external computing unit loads a new load value into the load register by using the new correction value stored in the calibration register to deduce the new load value therefrom.

Abstract translation: 一种具有时钟校准装置的集成电路，其接收来自振荡器的本地时钟信号，并向该信号施加校正值以产生经校正的时钟信号。 时钟校准装置包括具有可编程分频器和用于存储校正值的校准寄存器的分频模块，可编程分频器接收本地时钟信号并传送校正后的时钟信号，以及用于使用外部电路确定新校正值的电路 参考信号。 时基单元使用从本地时钟信号导出的定时信号产生时基信号，并且其包括耦合到负载寄存器的计数模块，其中存储负载值，其确定时基信号的频率与时基信号的频率之间的比率 定时信号的。 外部计算单元通过使用存储在校准寄存器中的新校正值将新的负载值加载到装载寄存器中，从而推断出新的负载值。

公开(公告)号：US07043628B2

公开(公告)日：2006-05-09

申请号：US09995251

申请日：2001-11-27

Applicant: Franck Roche ,  Pascal Narche ,  Ludovic Ruat

Inventor： Franck Roche ,  Pascal Narche ,  Ludovic Ruat

IPC: G06F9/00

CPC classification number: G06F11/2273 ,  G01R31/31701 ,  G01R31/31719

Abstract: A microprocessor includes a counter having a counting input and a reset input. The counting input is coupled to a first terminal of the microprocessor for the selection of an operating mode thereof by application of a predetermined number of pulses to the first terminal. The reset input of the counter is driven by a control signal present on a second terminal of the microprocessor. The control signal is maintained by default at a first logic value ensuring the maintaining at zero of the counter during the initialization period by a circuit internal or external the microprocessor. Immunity against electromagnetic perturbations causing the microprocessor to enter into the test mode is provided.

Abstract translation: 微处理器包括具有计数输入和复位输入的计数器。 计数输入耦合到微处理器的第一端，用于通过向第一终端施加预定数量的脉冲来选择其操作模式。 计数器的复位输入由存在于微处理器的第二端子上的控制信号驱动。 控制信号默认维持在第一逻辑值，确保在初始化期间通过内部或外部微处理器的电路将计数器保持在零。 提供了防止导致微处理器进入测试模式的电磁扰动的抗扰度。

公开(公告)号：US20050044276A1

公开(公告)日：2005-02-24

申请号：US10493039

申请日：2002-10-11

Applicant: Ludovic Ruat ,  Paul Kinowski ,  Alexander Czajor

Inventor： Ludovic Ruat ,  Paul Kinowski ,  Alexander Czajor

IPC: G06F13/38 ,  G06F3/00

CPC classification number: G06F13/385

Abstract: A device for receiving asynchronous frames beginning with a header field, the device including a circuit for switching into a stand-by mode, a circuit for recognizing a header field, and a circuit for leaving the stand-by mode when a valid header field is recognized, the stand-by mode including the filtering of at least one signal likely to be emitted by the receiver device during the reception of a header field. The device is suitable in particular for UART circuits that are present in microcontrollers.

Abstract translation: 一种用于从标题字段开始接收异步帧的装置，该装置包括用于切换到待机模式的电路，用于识别报头字段的电路，以及当有效报头字段为有效报头字段时离开待机模式的电路 识别，待机模式包括在接收报头字段期间对接收机设备可能发射的至少一个信号进行滤波。 该器件特别适用于存在于微控制器中的UART电路。

公开(公告)号：US06772946B2

公开(公告)日：2004-08-10

申请号：US10059444

申请日：2002-01-29

Applicant: Ludovic Ruat ,  Olivier Ferrand ,  Bruno Gailhard

Inventor： Ludovic Ruat ,  Olivier Ferrand ,  Bruno Gailhard

IPC: G06K1906

CPC classification number: G06K7/0069 ,  G06K7/0013 ,  G06K7/006 ,  G06K7/0086 ,  Y10T307/937

Abstract: A smart card reader includes a housing for receiving a smart card, a microprocessor, and a connector for connecting the microprocessor to the received smart card for establishing communications therebetween. A voltage source provides a power supply voltage to the microprocessor based upon the smart card being received in the housing. The smart card reader further includes a first switch interposed between the voltage source and a power supply terminal of the microprocessor. The first switch is closed when the received smart card is at an end of travel in the housing so that the power supply voltage is provided to the microprocessor, and is opened when the received smart card is no longer at the end of travel in the housing so that the power supply voltage is not provided to the microprocessor.

Abstract translation: 智能卡读取器包括用于接收智能卡的壳体，微处理器和用于将微处理器连接到接收的智能卡的连接器，用于在其间建立通信。 电压源基于智能卡被接收在外壳中而向微处理器提供电源电压。 智能卡读卡器还包括插入在电压源和微处理器的电源端之间的第一开关。 当接收到的智能卡处于壳体行程结束时，第一开关闭合，使得电源电压被提供给微处理器，并且当接收到的智能卡不再在外壳中行进结束时打开 使得不向微处理器提供电源电压。