利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

15 条记录 (耗时 0.036 秒)

    Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participants
    1.
    发明授权
    Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participants 有权
    多处理器高速缓存一致性系统和方法，其中处理器节点和输入/输出节点是相等的参与者

    公开(公告)号：US06925537B2

    公开(公告)日：2005-08-02

    申请号：US10698130

    申请日：2003-10-31

    申请人： Luiz A. Barroso ,  Kourosh Gharachorloo ,  Andreas Nowatzyk ,  Mosur K. Ravishankar ,  Robert J. Stets, Jr.

    发明人： Luiz A. Barroso ,  Kourosh Gharachorloo ,  Andreas Nowatzyk ,  Mosur K. Ravishankar ,  Robert J. Stets, Jr.

    IPC分类号： G06F12/08 ,  G06F12/00

    CPC分类号： G06F12/0817 ,  G06F2212/621

    摘要： A computer system has a plurality of processor nodes and a plurality of input/output nodes. Each processor node includes a multiplicity of processor cores, an interface to a local memory system and a protocol engine implementing a predefined cache coherence protocol. Each processor core has an associated memory cache for caching memory lines of information. Each input/output node includes no processor cores, an input/output interface for interfacing to an input/output bus or input/output device, a memory cache for caching memory lines of information and an interface to a local memory subsystem. The local memory subsystem of each processor node and input/output node stores a multiplicity of memory lines of information. The protocol engine of each processor node and input/output node implements the same predefined cache coherence protocol.

    摘要翻译： 计算机系统具有多个处理器节点和多个输入/输出节点。 每个处理器节点包括多个处理器核心，到本地存储器系统的接口和实现预定义高速缓存一致性协议的协议引擎。 每个处理器核心具有用于缓存存储器信息线的相关联的存储器缓存。 每个输入/输出节点不包括处理器内核，用于与输入/输出总线或输入/输出设备进行接口的输入/输出接口，用于缓存存储器信息线的存储器缓存和到本地存储器子系统的接口。 每个处理器节点和输入/输出节点的本地存储器子系统存储多个存储器信息线。 每个处理器节点和输入/输出节点的协议引擎实现相同的预定义缓存一致性协议。

    System and method for limited fanout daisy chaining of cache invalidation requests in a shared-memory multiprocessor system
    2.
    发明授权
    System and method for limited fanout daisy chaining of cache invalidation requests in a shared-memory multiprocessor system 有权
    用于在共享内存多处理器系统中缓存无效请求的有限扇出菊花链的系统和方法

    公开(公告)号：US07389389B2

    公开(公告)日：2008-06-17

    申请号：US10672960

    申请日：2003-09-26

    申请人： Kourosh Gharachorloo ,  Luiz A. Barroso ,  Robert J. Stets, Jr. ,  Mosur K. Ravishankar ,  Andreas Nowatzyk

    发明人： Kourosh Gharachorloo ,  Luiz A. Barroso ,  Robert J. Stets, Jr. ,  Mosur K. Ravishankar ,  Andreas Nowatzyk

    IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F7/00 ,  G06F15/16

    CPC分类号： G06F12/0826 ,  G06F2212/621 ,  Y10S707/99952

    摘要： A protocol engine is for use in each node of a computer system having a plurality of nodes. Each node includes an interface to a local memory subsystem that stores memory lines of information, a directory, and a memory cache. The directory includes an entry associated with a memory line of information stored in the local memory subsystem. The directory entry includes an identification field for identifying sharer nodes that potentially cache the memory line of information. The identification field has a plurality of bits at associated positions within the identification field. Each respective bit of the identification field is associated with one or more nodes. The protocol engine furthermore sets each bit in the identification field for which the memory line is cached in at least one of the associated nodes. In response to a request for exclusive ownership of a memory line, the protocol engine sends an initial invalidation request to no more than a first predefined number of the nodes associated with set bits in the identification field of the directory entry associated with the memory line.

    摘要翻译： 协议引擎用于具有多个节点的计算机系统的每个节点。 每个节点包括存储信息存储线，目录和存储器高速缓存的本地存储器子系统的接口。 目录包括与存储在本地存储器子系统中的信息的存储器线相关联的条目。 目录条目包括用于识别可能缓存信息的存储器线的共享者节点的标识字段。 识别字段在识别字段内的关联位置具有多个位。 识别字段的每个相应位与一个或多个节点相关联。 协议引擎还将存储线被高速缓存的标识字段中的每一位设置在相关联的节点中的至少一个中。 响应于对存储器线路的独占所有权的请求，协议引擎将初始无效请求发送到与存储器线相关联的目录条目的标识字段中与设置位相关联的不超过第一预定数量的节点。

    Scalable multiprocessor system and cache coherence method
    5.
    发明授权
    Scalable multiprocessor system and cache coherence method 失效
    可扩展的多处理器系统和缓存一致性方法

    公开(公告)号：US06751710B2

    公开(公告)日：2004-06-15

    申请号：US09878982

    申请日：2001-06-11

    申请人： Kourosh Gharachorloo ,  Luiz A. Barroso ,  Mosur K. Ravishankar ,  Robert J. Stets, Jr. ,  Daniel J. Scales

    发明人： Kourosh Gharachorloo ,  Luiz A. Barroso ,  Mosur K. Ravishankar ,  Robert J. Stets, Jr. ,  Daniel J. Scales

    IPC分类号： G06F1200

    CPC分类号： G06F12/0826 ,  G06F12/0828 ,  G06F2212/621

    摘要： The present invention relates generally to multiprocessor computer system, and particularly to a multiprocessor system designed to be highly scalable, using efficient cache coherence logic and methodologies. More specifically, the present invention is a system and method including a plurality of processor nodes configured to execute a cache coherence protocol that avoids the use of negative acknowledgment messages (NAKs) and ordering requirements on the underlying transaction-message interconnect/network and services most 3-hop transactions with only a single visit to the home node.

    摘要翻译： 本发明一般涉及多处理器计算机系统，特别涉及使用有效的高速缓存一致性逻辑和方法来设计为高度可扩展的多处理器系统。 更具体地说，本发明是一种包括多个处理器节点的系统和方法，所述多个处理器节点被配置为执行避免使用否定确认消息（NAK）的高速缓存一致性协议以及对底层事务 - 消息互联/网络和服务的排序要求 只有一次访问家庭节点的3跳交易。

    Method and system for detecting and resolving virtual address synonyms in a two-level cache hierarchy
    6.
    发明授权
    Method and system for detecting and resolving virtual address synonyms in a two-level cache hierarchy 失效
    用于检测和解析两级缓存层次结构中的虚拟地址同义词的方法和系统

    公开(公告)号：US06751720B2

    公开(公告)日：2004-06-15

    申请号：US10042054

    申请日：2002-01-07

    申请人： Luiz André Barroso ,  Kourosh Gharachorloo ,  Andreas Nowatzyk ,  Robert J. Stets, Jr. ,  Mosur Kumaraswamy Ravishankar

    发明人： Luiz André Barroso ,  Kourosh Gharachorloo ,  Andreas Nowatzyk ,  Robert J. Stets, Jr. ,  Mosur Kumaraswamy Ravishankar

    IPC分类号： G06F1200

    CPC分类号： G06F12/0826 ,  G06F12/0828 ,  G06F2212/621

    摘要： L1 cache synonyms in a two-level cache system are detected and resolved by logic in the L2 cache. Duplicate copies of the L1 cache tags and state (“Dtags”) are maintained in the L2 cache. After a miss occurs in the L1 cache, the Dtags in the second-level cache that correspond to all possible synonym locations in the L1 cache are searched for synonyms. If a synonym is found, the L2 cache notifies the L1 cache where the requested cache line can be found in the L1 cache. The L1 cache then copies the cache line from the location where the synonym was found to the location where the miss occurred, and it invalidates the cache line at the original location. The Dtags in the second-level cache are updated to reflect the changes made in the L1 cache.

    摘要翻译： 二级缓存系统中的L1缓存同义词通过L2缓存中的逻辑进行检测和解析。 L1缓存标签和状态（“Dtags”）的重复副本被保留在L2高速缓存中。 在L1高速缓存中出现未命中之后，搜索对应于L1高速缓存中所有可能的同义词位置的二级高速缓存中的Dtags同义词。 如果发现同义词，则L2缓存通知L1缓存，其中可以在L1缓存中找到所请求的高速缓存行。 然后，L1高速缓存从发现同义词的位置复制缓存行到发生未命中的位置，并且使原始位置的高速缓存行无效。 更新二级缓存中的Dtags以反映L1缓存中所做的更改。

    Search result inputs using variant generalized queries
    7.
    发明授权
    Search result inputs using variant generalized queries 有权
    使用变体广义查询搜索结果输入

    公开(公告)号：US09110975B1

    公开(公告)日：2015-08-18

    申请号：US11556100

    申请日：2006-11-02

    申请人： Michelangelo Diligenti ,  Hyung-Jin Kim ,  Robert J. Stets, Jr.

    发明人： Michelangelo Diligenti ,  Hyung-Jin Kim ,  Robert J. Stets, Jr.

    IPC分类号： G06F17/30

    CPC分类号： G06F17/30646 ,  G06F17/30864

    摘要： Systems, methods and computer program products for generalizing a user-submitted query by forming one or more variants of the user-submitted query to generate one or more other queries, each of the one or more other queries being different from the user-submitted query. A generalized quality of result statistic is derived for a first document from respective data associated with each of the other queries, each respective data being indicative of user behavior relative to the first document as a search result for the associated other query. The generalized quality of result statistic is provided as the quality of result statistic input to a document ranking process for the first document and the user-submitted query.

    摘要翻译： 用于通过形成用户提交的查询的一个或多个变体来概括用户提交的查询以生成一个或多个其他查询的一个或多个其他查询中的每一个与用户提交的查询不同的系统，方法和计算机程序产品 。 从与每个其他查询相关联的相应数据的第一文档导出结果统计量的一般化质量，每个相应数据指示相对于第一文档的用户行为作为相关联的其他查询的搜索结果。 提供结果统计量的广义质量作为第一个文档和用户提交的查询的文档排序过程的结果统计输入的质量。

    Modifying search result ranking based on a temporal element of user feedback
    9.
    发明授权
    Modifying search result ranking based on a temporal element of user feedback 有权
    基于用户反馈的时间要素修改搜索结果排序

    公开(公告)号：US09092510B1

    公开(公告)日：2015-07-28

    申请号：US11742447

    申请日：2007-04-30

    申请人： Robert J. Stets, Jr. ,  Mark Andrew Paskin

    发明人： Robert J. Stets, Jr. ,  Mark Andrew Paskin

    IPC分类号： G06F17/30 ,  G06F7/00

    CPC分类号： G06F17/30648 ,  G06F17/30064

    摘要： In general, the subject matter described in this specification can be embodied in a method that includes: obtaining user feedback associated with quality of an electronic document; adjusting a measure of relevance for the electronic document based on a temporal element of the user feedback; and outputting the measure of relevance to a ranking engine for ranking of search results, including the electronic document, for a search for which the electronic document is returned. Obtaining the user feedback can include receiving user selections of documents presented by a document search service, the method can include evaluating the user selections in accordance with an implicit user feedback model to determine the measure of relevance, and adjusting the measure of relevance can include adjusting the measure of relevance in accordance with the implicit user feedback model.

    摘要翻译： 通常，本说明书中描述的主题可以包括：获得与电子文档的质量相关联的用户反馈的方法; 基于所述用户反馈的时间要素调整所述电子文档的相关性度量; 并输出与包括电子文档在内的搜索结果排序的排名引擎相关的度量，用于返回电子文档的搜索。 获取用户反馈可以包括接收由文档搜索服务呈现的文档的用户选择，该方法可以包括根据隐含的用户反馈模型来评估用户选择，以确定相关性的度量，并且调整相关性的度量可以包括调整 根据隐性用户反馈模型的相关度度量。

    Power-aware adaptation in a data center
    10.
    发明授权
    Power-aware adaptation in a data center 有权
    数据中心的电源感知适配

    公开(公告)号：US07546475B2

    公开(公告)日：2009-06-09

    申请号：US10436849

    申请日：2003-05-13

    申请人： Robert N. Mayo ,  Parthasarathy Ranganathan ,  Robert J. Stets, Jr. ,  Deborah A. Wallach

    发明人： Robert N. Mayo ,  Parthasarathy Ranganathan ,  Robert J. Stets, Jr. ,  Deborah A. Wallach

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3203 ,  G06F1/329 ,  Y02D10/24

    摘要： A data center is disclosed with power-aware adaptation that minimizes the performance impact of reducing the power consumption of individual nodes in the data center. A data center according to the present techniques includes a request redirector that obtains an access request for data stored on a set of storage devices and that distributes the access request to one of a set of access nodes in response to a priority of the access request and a rank of each access node. A data center according to the present techniques also includes a power manager that performs a power adaptation in the data center by selecting access nodes for power reduction based on the ranks of the access nodes. The judicious distribution of access requests to appropriately ranked nodes and the judicious selection of access nodes for power reduction enhances the likelihood that higher priority cached data is not lost during power adaptation.

    摘要翻译： 公开了具有功率感知适配的数据中心，其最小化了降低数据中心中各个节点的功耗的性能影响。 根据本技术的数据中心包括：请求重定向器，其获取存储在一组存储设备上的数据的访问请求，并且响应于访问请求的优先级将访问请求分发到一组接入节点中的一个;以及 每个接入节点的等级。 根据本技术的数据中心还包括功率管理器，其通过基于接入节点的等级选择用于功率降低的接入节点来在数据中心中执行功率调整。 对适当排名的节点的访问请求的明智分配以及用于功率降低的接入节点的明智选择增强了在电力适配期间较高优先级的高速缓存数据不会丢失的可能性。