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公开(公告)号：US11218345B2
公开(公告)日：2022-01-04
申请号：US17026041
申请日：2020-09-18
摘要： A method and apparatus for processing a signal to generate equalizer codes, which are used to control equalization of the signal, that comprises processing the signal to identify the eyes of the signal, and for each eye, calculating an eye height and calculating a noise value. For each eye, squaring the eye height to generate an eye height product and dividing the eye height product by the noise value to generate a Q2 value. Using the calculated Q2 values optimizing, through adaptation, the equalizer codes. Calculating the noise values may include calculating an ISI value for each band of the signal and then calculating the eye height for each eye as the difference between the adjacent upper average value and the adjacent lower average value. Then, for each eye, calculating a noise value by summing the ISI value for the band above the eye and the band below the eye.
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公开(公告)号：US11411653B2
公开(公告)日：2022-08-09
申请号：US17124430
申请日：2020-12-16
发明人： Eric Lozsef , George L. Barrier, IV
IPC分类号： H04B10/524 , H04B10/58 , H04B10/079 , H04B10/50
摘要： Techniques for automatically determining an input resistance of an optical modulator and configuring a modulation current source can include applying a first bias current to an input of the optical transmitter and measuring a corresponding first voltage at the input of the optical transmitter. A second bias current can also be applied to the input of the optical transmitter and a corresponding second voltage at the input of the optical transmitter can be measured. An input resistance of the specific optical transmitter can be determined from the difference between the first and second voltages divided by the difference between the first and second bias currents. The technique can further include setting one or more configuration settings in one or more registers of a modulation current source based on the determined input resistance of the optical transmitter. Thereafter, the output modulation current for driving the specific optical transmitter can be configured based on the one or more configuration settings in the one or more registers.
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公开(公告)号：US20210152143A1
公开(公告)日：2021-05-20
申请号：US17158974
申请日：2021-01-26
摘要： A system to control convergence of a loop to a reference value. A device, under control of the control loop, generates an output signal. A comparator compares the output signal to a reference value. Responsive to the output signal being less than the reference value, outputting an up signal and, responsive to the output signal being greater than the reference value, outputting a down signal. A counter is configured to maintain a counter value which is incremented in response to an up signal and decremented in response to a down signal. The counter outputs a gain control value. An up/down signal tracker is configured to track a pattern of up signals and down signals and compare the tracked pattern to one or more predetermined patterns such that, responsive to the up signals and down signals matching one of the one or more predetermined patterns, the counter size is decreased.
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公开(公告)号：US10911052B2
公开(公告)日：2021-02-02
申请号：US16421376
申请日：2019-05-23
IPC分类号： H03L7/081 , H04L27/227 , G04F10/00 , G06F1/06 , G06F1/12 , G06F1/10 , H04L25/49 , H04L7/033 , H04L27/38 , H04L7/00
摘要： A system for retiming a multi-level signal that forms an eye diagram when plotted, such as a PAM4 signal that includes an equalizer configured to create an equalized signal and a first amplifier configured to amplify the equalized signal, responsive to a first amplifier control signal, to create a first amplified signal, and a second amplifier configured to amplify the equalized signal, responsive to a second amplifier control signal, to create a second amplified signal. An eye monitor processes the equalized signal, the first amplified signal, and the second amplified signal to create a first retiming clock phase signal and a second retiming clock phase signal, which control sampling times for flip-flops. One or more delays and one or more emphasis modules are configured to delay and introduce emphasis into an output from the flip-flops, the resulting signals are combined in a summing junction to create the retimed signal.
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公开(公告)号：US20200007133A1
公开(公告)日：2020-01-02
申请号：US16421376
申请日：2019-05-23
摘要： A system for retiming a multi-level signal that forms an eye diagram when plotted, such as a PAM4 signal that includes an equalizer configured to create an equalized signal and a first amplifier configured to amplify the equalized signal, responsive to a first amplifier control signal, to create a first amplified signal, and a second amplifier configured to amplify the equalized signal, responsive to a second amplifier control signal, to create a second amplified signal. An eye monitor processes the equalized signal, the first amplified signal, and the second amplified signal to create a first retiming clock phase signal and a second retiming clock phase signal, which control sampling times for flip-flops. One or more delays and one or more emphasis modules are configured to delay and introduce emphasis into an output from the flip-flops, the resulting signals are combined in a summing junction to create the retimed signal.
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公开(公告)号：US11196484B2
公开(公告)日：2021-12-07
申请号：US17071801
申请日：2020-10-15
IPC分类号： H04B10/69 , H04B10/079
摘要： An improved method and system for locating a slicer threshold and phase is disclosed. A two-dimensional field of coordinates is defined using phase versus eye monitor magnitude. At each coordinate, the number of samples above the eye monitor magnitude are counted. Dividing by the total number of samples considered yields a ratio between 0 and 1. Each eye 0, 1, 2 (bottom, middle, top in a PAM4 system) has an ideal ratio (75%, 50%, 25%) assuming a balanced distribution of PAM4 levels. The rating (third dimension) at each coordinate is calculated to be (0.25−abs.value (actual_ratio−ideal_ratio)) limited to positive results only. The resulting ratings are summed over phase. The eye center is calculated using weighted average of the sums. The eye center is compared to the calibrated target to determine which way to move the slicer threshold.
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公开(公告)号：US20210111793A1
公开(公告)日：2021-04-15
申请号：US17071801
申请日：2020-10-15
IPC分类号： H04B10/079
摘要： An improved method and system for locating a slicer threshold and phase is disclosed. A two-dimensional field of coordinates is defined using phase versus eye monitor magnitude. At each coordinate, the number of samples above the eye monitor magnitude are counted. Dividing by the total number of samples considered yields a ratio between 0 and 1. Each eye 0, 1, 2 (bottom, middle, top in a PAM4 system) has an ideal ratio (75%, 50%, 25%) assuming a balanced distribution of PAM4 levels. The rating (third dimension) at each coordinate is calculated to be (0.25−abs.value (actual_ratio−ideal_ratio)) limited to positive results only. The resulting ratings are summed over phase. The eye center is calculated using weighted average of the sums. The eye center is compared to the calibrated target to determine which way to move the slicer threshold.
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公开(公告)号：US10938365B2
公开(公告)日：2021-03-02
申请号：US16417513
申请日：2019-05-20
摘要： A system for controlling convergence of gain to a target value for a variable gain amplifier comprising a detector module configured to determine a magnitude value of a variable gain amplifier output. Also, part of this embodiment is a comparator module configured to compare the magnitude value to a target value and responsive to the comparison, generate an up_dn signal. A digital control module is configured to receive the up_dn signal and processes the up_dn signal to generate a control vector. One or more digital to analog converters are configured to convert the control vector to an analog control signal such that the analog control signal controls the gain of the variable gain amplifier. Various methods of operation exist for this hardware configured to improve convergence time to a target gain value while controlling the rate of change of the gain.
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公开(公告)号：US20190356292A1
公开(公告)日：2019-11-21
申请号：US16417513
申请日：2019-05-20
IPC分类号： H03G3/30
摘要： A system for controlling convergence of gain to a target value for a variable gain amplifier comprising a detector module configured to determine a magnitude value of a variable gain amplifier output. Also, part of this embodiment is a comparator module configured to compare the magnitude value to a target value and responsive to the comparison, generate an up_dn signal. A digital control module is configured to receive the up_dn signal and processes the up_dn signal to generate a control vector. One or more digital to analog converters are configured to convert the control vector to an analog control signal such that the analog control signal controls the gain of the variable gain amplifier. Various methods of operation exist for this hardware configured to improve convergence time to a target gain value while controlling the rate of change of the gain.
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