公开(公告)号：US12230701B2

公开(公告)日：2025-02-18

申请号：US18099293

申请日：2023-01-20

Applicant: MACOM Technology Solutions Holdings, Inc.

Inventor： Khaled Fayed ,  Simon Wood

IPC: H01L29/778 ,  H01L23/522 ,  H01L23/528 ,  H01L29/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/417 ,  H01L29/423

Abstract: A transistor includes a plurality of gate fingers that extend in a first direction and are spaced apart from each other in a second direction, each of the gate fingers comprising at least spaced-apart and generally collinear first and second gate finger segments that are electrically connected to each other. The first gate finger segments are separated from the second gate finger segments in the first direction by a gap region that extends in the second direction. A resistor is disposed in the gap region.

公开(公告)号：US20250047252A1

公开(公告)日：2025-02-06

申请号：US18292231

申请日：2022-08-31

Applicant: MACOM Technology Solutions Holdings, Inc.

Inventor： Duy NGUYEN ,  Ray MORONEY ,  Stefano D'AGOSTINO ,  Trong PHAN

IPC: H03F3/45

Abstract: Aspects of an amplifier with bias stabilization are described. In one example, an amplifier includes an output amplifier stage having an input terminal, a biasing leg having a biasing node coupled to the input terminal, and a bias feedback network coupled between the input terminal of the output amplifier stage and the biasing leg. The bias feedback network can include a difference amplifier, a bypass stage, and a reference voltage generator in one example. The difference amplifier can generate a bias control signal based on a difference between a bias voltage at a base terminal of the output amplifier stage and a voltage reference generated by the reference voltage generator. The bias feedback network generates the bias control signal and controls the bias voltage based on feedback, to keep the bias voltage and bias current constant over process, temperature, gain and other variations for consistent performance.

公开(公告)号：US20250030483A1

公开(公告)日：2025-01-23

申请号：US18224760

申请日：2023-07-21

Applicant: MACOM Technology Solutions Holdings, Inc.

Inventor： Eric Iozsef ,  Rajiv Shukla

IPC: H04B10/40 ,  H04B10/25 ,  H04B10/50

Abstract: An architecture for peripheral component interconnect express compliant signals over optical fiber is provided. A method includes, based on a first determination that an impedance level of a receiver device satisfies a defined impedance level, causing a driver to pulse at a first defined frequency and duty cycle level. Further, based on a second determination that a number of pulses received, at a transimpedance amplifier, at the first defined frequency and duty cycle level satisfy a defined number of pulses and at least one defined criterion, the method causes a second impedance level of the driver to match the defined impedance level and causes the driver to enter an electrical idle state. The method also includes facilitating, by a transmitter, transmission of data to the receiver device at a second defined frequency level, via an optical fiber link.

公开(公告)号：US20250007479A1

公开(公告)日：2025-01-02

申请号：US18214660

申请日：2023-06-27

Applicant: MACOM Technology Solutions Holdings, Inc.

Inventor： Vasilis Papanikolaou

IPC: H03G3/30 ,  H03F1/32 ,  H03F3/45

Abstract: Adjustments to gain levels, associated with amplifiers, including partial adjustments to gain levels associated with certain amplifiers can be controlled and performed in accordance with an amplifier gain adjustment sequence. In response to determining that an overall gain level associated with a group of amplifiers, comprising first, second, and third amplifiers, is to be reduced, AGC component can determine whether a third gain level associated with the third amplifier is at a minimum. In response to determining that third gain level is at minimum, AGC component can determine which of a first gain level associated with the first amplifier and a second gain level associated with the second amplifier is to be partially reduced, in accordance with the amplifier gain adjustment sequence that, in part, specifies alternating between partial first gain level reductions associated with the first amplifier and partial second gain level reductions associated with the second amplifier.

公开(公告)号：US12136901B2

公开(公告)日：2024-11-05

申请号：US17517170

申请日：2021-11-02

Applicant: MACOM Technology Solutions Holdings, Inc.

Inventor： Bi Ngoc Pham ,  Gerard Bouisse

IPC: H03F1/02 ,  H03F1/08 ,  H03F1/42 ,  H03F3/21 ,  H03F3/213

Abstract: Apparatus and methods for a no-load-modulation power amplifier are described. No-load-modulation power amplifiers can comprise multiple amplifiers connected in parallel to amplify a signal that has been divided into parallel circuit branches. One of the amplifiers can operate as a main amplifier in a first amplification class and the remaining amplifiers can operate as peaking amplifiers in a second amplification class. The main amplifier can see essentially no modulation of its load between the power amplifier's fully-on and fully backed-off states. The power amplifiers can operate in symmetric and asymmetric modes. Improvements in bandwidth and drain efficiency over conventional Doherty amplifiers are obtained. Further improvements can be obtained by combining signals from the amplifiers with hybrid couplers.

公开(公告)号：US20240363742A1

公开(公告)日：2024-10-31

申请号：US18309320

申请日：2023-04-28

Applicant: MACOM Technology Solutions Holdings, Inc.

Inventor： Debdas Pal ,  Parshant Kumar ,  Stephen Bilotta ,  Timothy E. Boles

IPC: H01L29/737 ,  H01L29/06

CPC classification number: H01L29/737 ,  H01L29/0619

Abstract: The reduction of feedback capacitance in active semiconductor devices, such as the reduction in collector to base capacitance in transistors, is described. In one example, a transistor includes a substrate, an active region of the transistor in the substrate, a dielectric layer over a top surface of the substrate, and an interconnect region. The active region includes a base contact over the active region. The interconnect region includes a conductive interconnect that extends over the dielectric layer and is electrically coupled with the base contact. The interconnect region also includes a semiconductor junction region extending under the conductive interconnect in an area of the substrate outside of the active region. The addition of the semiconductor junction region under the conductive interconnect reduces the total collector to base capacitance in the transistor.

公开(公告)号：US12100630B2

公开(公告)日：2024-09-24

申请号：US17097294

申请日：2020-11-13

Applicant: MACOM Technology Solutions Holdings, Inc.

Inventor： Marvin Marbell ,  Melvin Nava ,  Jeremy Fisher ,  Alexander Komposch

IPC: H01L23/047 ,  H01L21/48 ,  H01L23/66

CPC classification number: H01L23/047 ,  H01L21/4817 ,  H01L23/66 ,  H01L2223/6611 ,  H01L2223/6655

Abstract: A radio frequency (RF) transistor amplifier includes a package submount. a package frame comprising an electrically insulating member and one or more conductive layers on the package submount and exposing a surface thereof, a transistor die on the surface of the package submount and comprising respective terminals that are electrically connected to the package frame, a protective member covering the transistor die, and one or more electrical components that are attached to the package frame outside the protective member. Related RF power device packages and fabrication methods are also discussed.

公开(公告)号：US12082342B2

公开(公告)日：2024-09-03

申请号：US17807037

申请日：2022-06-15

Applicant: MACOM Technology Solutions Holdings, Inc.

Inventor： Rathnait Long ,  Richard Allen Cory ,  Gerald Comtois ,  Scott Donahue

IPC: H05K1/18 ,  H05K1/02

CPC classification number: H05K1/184 ,  H05K1/0224 ,  H05K2201/09227 ,  H05K2201/10984

Abstract: Examples of printed circuit boards (PCBs) with board configuration blocks and board edge projections are described. In one example, a PCB includes a core material and a metal layer comprising a plurality of metal traces on the core material. The plurality of metal traces can include component interconnect traces and a board configuration block. The board configuration block can include a plan diagram for the PCB, an operational diagram for the PCB, or a combination of plan and operational diagrams. In other examples, a PCB can include a core material having a peripheral edge. The peripheral edge can include one or more board edge scheme projections positioned within projection edge regions of the peripheral edge. The scheme projections have a projection shape based on operational characteristics for the PCB. In some cases, the board configuration blocks can be located on the board edge scheme projections.

公开(公告)号：US12074123B2

公开(公告)日：2024-08-27

申请号：US17031745

申请日：2020-09-24

Applicant: MACOM Technology Solutions Holdings, Inc.

Inventor： Richard Wilson ,  Madhu Chidurala

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/498 ,  H01L25/18

CPC classification number: H01L23/66 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/08 ,  H01L24/48 ,  H01L25/18 ,  H01L2223/6672 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/16145 ,  H01L2224/48137 ,  H01L2224/48157

Abstract: A multi-level radio frequency (RF) integrated circuit component includes an upper level including at least one inductor, and a lower level including at least one conductive element that provides electrical connection to the at least one inductor. The lower level separates the at least one inductor from a lower surface that is configured to be attached to a conductive pad. Related integrated circuit device packages are also discussed.

公开(公告)号：US20240283122A1

公开(公告)日：2024-08-22

申请号：US18649368

申请日：2024-04-29

Applicant: MACOM Technology Solutions Holdings, Inc.

Inventor： Andrzej Rozbicki ,  Paul Hogan ,  Gary Pepelis ,  Scott Donahue

IPC: H01P5/08 ,  H01P5/02

CPC classification number: H01P5/085 ,  H01P5/028

Abstract: Aspects of coaxial to microstrip transitional housings are described. A method of forming a transitional housing includes forming a channel to a first depth into a housing block from a top surface of the housing block, forming a first annular opening to a second depth into the housing block from the top surface of the housing block at a first end of the channel, forming a second annular opening to the second depth into the housing block from the top surface of the housing block at a second end of the channel, inserting a first cylindrical plug into the first annular opening, and inserting a second cylindrical plug into the second annular opening. The second depth can be greater than the first depth in some cases.