DIE STRUCTURE, CONTACT TEST STRUCTURE, AND CONTACT TESTING METHOD UTILIZING THE CONTACT TEST STRUCTURE
    1.
    发明申请
    DIE STRUCTURE, CONTACT TEST STRUCTURE, AND CONTACT TESTING METHOD UTILIZING THE CONTACT TEST STRUCTURE 审中-公开
    DIE结构,接触测试结构和接触测试方法利用接触测试结构

    公开(公告)号:US20160041201A1

    公开(公告)日:2016-02-11

    申请号:US14456827

    申请日:2014-08-11

    CPC classification number: G01R31/307 G01R31/026 G01R31/2884

    Abstract: A die structure is described, including a device area and a contact test area. The device area has therein a device structure including a first contact plug. The contact test area has therein a contact test structure that includes a second contact plug and is different from the device structure. The contact test structure is also described, including a well, a heavily doped region in the well, and a contact plug, wherein the heavily doped region and the well are both of N-type or are both of P-type, and the contact plug is disposed over the heavily doped region.

    Abstract translation: 描述了一种模具结构,包括设备区域和接触测试区域。 装置区域具有包括第一接触插塞的装置结构。 接触测试区域具有包括第二接触插塞并且与器件结构不同的接触测试结构。 还描述了接触测试结构,包括阱,阱中的重掺杂区域和接触插塞,其中重掺杂区域和阱都是N型或都是P型,并且接触 插头设置在重掺杂区域上。

    METHOD, SYSTEMS, AND DEVICES FOR INSPECTING SEMICONDUCTOR DEVICES
    2.
    发明申请
    METHOD, SYSTEMS, AND DEVICES FOR INSPECTING SEMICONDUCTOR DEVICES 审中-公开
    用于检查半导体器件的方法,系统和器件

    公开(公告)号:US20150293169A1

    公开(公告)日:2015-10-15

    申请号:US14252583

    申请日:2014-04-14

    CPC classification number: G01R31/2653 G01R31/2656

    Abstract: Present example embodiments relate generally to methods, logic, systems, and devices for inspecting a semiconductor device. Example methods comprise applying an initial energy from an energy source to a first location of a conductive layer of the semiconductor device. Example methods further comprise measuring a resultant energy passing through the conductive layer using a probe at a second location of the conductive layer and analyzing the measured resultant energy passing through the conductive layer. Example methods further comprise determining a presence of an inconsistency in the conductive layer based on the analyzing.

    Abstract translation: 本示例实施例一般涉及用于检查半导体器件的方法,逻辑,系统和设备。 示例性方法包括将来自能量源的初始能量施加到半导体器件的导电层的第一位置。 示例性方法还包括使用在导电层的第二位置处的探针测量通过导电层的合成能量,并分析通过导电层的测量的合成能。 示例性方法还包括基于分析确定导电层中的不一致性的存在。

    TEST PATTERN DESIGN FOR SEMICONDUCTOR DEVICES AND METHOD OF UTILIZING THEREOF
    3.
    发明申请
    TEST PATTERN DESIGN FOR SEMICONDUCTOR DEVICES AND METHOD OF UTILIZING THEREOF 审中-公开
    半导体器件的测试图案设计及其使用方法

    公开(公告)号:US20140253137A1

    公开(公告)日:2014-09-11

    申请号:US13790253

    申请日:2013-03-08

    CPC classification number: H01L24/64 G01R31/2884 G01R31/307 H01L22/12 H01L22/30

    Abstract: Methods and systems for the detection of defects in semiconductors, semiconductor devices, or substrates are provided. Semiconductors, semiconductor devices or substrates having novel test patterns and or designs are also provided. The semiconductors, semiconductor devices or substrates have a plurality of line patterns, which, in response to a responsive stimulus such as electron beam irradiation, produces a response. The responsive stimulus may include an electron beam irradiation, and the image data can be collected and processed to produce an image or images that indicate the presence or absence of surface and/or internal defects.

    Abstract translation: 提供了用于检测半导体,半导体器件或衬底中的缺陷的方法和系统。 还提供了具有新颖测试图案和/或设计的半导体,半导体器件或衬底。 半导体,半导体器件或衬底具有多个线图案,其响应于诸如电子束照射的响应刺激而产生响应。 响应刺激可以包括电子束照射,并且可以收集和处理图像数据以产生指示表面和/或内部缺陷的存在或不存在的图像或图像。

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