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    Interconnect structure and fabricating method thereof
    1.
    发明授权
    Interconnect structure and fabricating method thereof 有权

    公开(公告)号：US10153233B1

    公开(公告)日：2018-12-11

    申请号：US15655596

    申请日：2017-07-20

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Chi-Hao Huang ,  Chin-Cheng Yang

    IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768

    Abstract: An interconnect structure including a first dielectric layer, a first conductive layer, a second conductive layer, a capping layer, and a via is provided. The first dielectric layer has a first trench and a second trench. The first conductive layer is located in the first trench. The second conductive layer is located in the second trench, and a top surface of the second conductive layer is lower than a top surface of the first dielectric layer. The capping layer having a via opening exposing a portion of the first conductive layer covers the first dielectric layer, the first conductive layer, and the second conductive layer. The via located on the first conductive layer and the first dielectric layer located between the first conductive layer and the second conductive layer is filled into the via opening and electrically connected to the first conductive layer.

    Layout design for fanout patterns in self-aligned double patterning process
    3.
    发明授权
    Layout design for fanout patterns in self-aligned double patterning process 有权

    公开(公告)号：US10497566B1

    公开(公告)日：2019-12-03

    申请号：US16012608

    申请日：2018-06-19

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Chin-Cheng Yang ,  Chi-Hao Huang ,  Wei-Hung Wang

    IPC: H01L21/033 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L27/105

    Abstract: A circuit structure comprises a plurality of first conducting lines extending in a first direction, the first conducting lines having a first pitch in a second direction orthogonal to the first direction; a plurality of linking lines extending in the second direction, the linking lines having a second pitch in the first direction, the second pitch being greater than the first pitch; and a plurality of connection structures connecting respective first conducting lines for current flow to respective linking lines, the connection structures each including a plurality of segments extending in the first direction, segments in the plurality of segments having a transition pitch in the second direction relative to adjacent segments in the plurality of segments greater than or equal to the first pitch, and less than the second pitch.

    SCANNER AND METHOD FOR PERFORMING EXPOSURE PROCESS ON WAFER
    4.
    发明申请
    SCANNER AND METHOD FOR PERFORMING EXPOSURE PROCESS ON WAFER 审中-公开
    扫描仪及其在曝光过程中的方法

    公开(公告)号：US20160048087A1

    公开(公告)日：2016-02-18

    申请号：US14457982

    申请日：2014-08-12

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Chin-Cheng Yang ,  Chi-Hao Huang

    IPC: G03F7/20

    CPC classification number: G03F7/707 ,  G03F7/70633 ,  G03F7/70708 ,  G03F7/70783 ,  G03F9/7011 ,  H01L21/682

    Abstract: A scanner and a method for performing an exposure process through a photomask on a wafer are provided. The exposure process includes an alignment step and an exposure step. The method includes the steps of moving a wafer table to align the wafer with an alignment apparatus, wherein the wafer table includes at least one chuck hole to attach the wafer to the wafer table by vacuum chucking, detecting an actual position of each of a plurality of alignment marks on the wafer, calculating an index value based on a difference between a predicted position and the actual position of each alignment mark, adjusting a vacuum pressure of the at least one chuck hole in the alignment step when the index value is larger than a first threshold value, and finishing the exposure process when the index value is smaller than or equal to the first threshold value.

    Abstract translation: 提供了扫描仪和通过晶片上的光掩模进行曝光处理的方法。 曝光过程包括对准步骤和曝光步骤。 该方法包括以下步骤：移动晶片台以使晶片与对准装置对准，其中晶片台包括至少一个卡盘孔，以通过真空夹紧将晶片附接到晶片台，检测多个实体中的每一个的实际位置 在所述晶片上的对准标记，基于预测位置和每个对准标记的实际位置之间的差异来计算指标值，当所述指标值大于所述对准步骤时，调整所述对准步骤中的所述至少一个卡盘孔的真空压力 第一阈值，并且当所述指标值小于或等于所述第一阈值时完成所述曝光处理。

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