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    SECURE MECHANISM IN SECURITY CHIP
    1.
    发明申请
    SECURE MECHANISM IN SECURITY CHIP 有权

    公开(公告)号：US20210057002A1

    公开(公告)日：2021-02-25

    申请号：US16850788

    申请日：2020-04-16

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Chia-Jung CHEN ,  Chin-Hung CHANG ,  Ken-Hui CHEN

    IPC: G11C7/10 ,  G11C7/12 ,  H04L9/06 ,  H04L9/32 ,  H04L29/06

    Abstract: A memory device, including a secure command decoder implementing security logic configured to detect commands carrying an encrypted immediate data payload from a requesting host, authenticate the host as source of the command, decode the immediate data and perform a memory access command called for by a command portion of the decrypted immediate data upon the storage cells of the memory device using the non-command portion of the decrypted immediate data, as well as to encrypt any result from executing the command portion prior to returning the result to the requesting host, and an input/output interface for I/O data units supporting multiple hosts.

    MEMORY DEVICE AND ASSOCIATED CONTROL METHOD
    4.
    发明公开
    MEMORY DEVICE AND ASSOCIATED CONTROL METHOD 审中-公开

    公开(公告)号：US20230251782A1

    公开(公告)日：2023-08-10

    申请号：US17817711

    申请日：2022-08-05

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Chin-Hung CHANG ,  Chia-Jung CHEN ,  Ken-Hui CHEN ,  Chun-Hsiung HUNG

    IPC: G06F3/06

    CPC classification number: G06F3/0622 ,  G06F3/0637 ,  G06F3/0679

    Abstract: A memory device and an associated control method are provided. The memory device includes a non-volatile memory array and a memory control circuit. The non-volatile memory array includes M secured memory zones. The memory control circuit is electrically connected to the non-volatile memory array. The memory control circuit provides a set of mapping information and searches a request key in the set of mapping information. The set of mapping information represents correspondences between N access keys and the M secured memory zones. The memory control circuit acquires at least one of the M secured memory zones if the request key is one of the N access keys, and performs an access command to the at least one of the M secured memory zones. M and N are positive integers.

    SECURITY MEMORY SCHEME
    5.
    发明申请
    SECURITY MEMORY SCHEME 有权

    公开(公告)号：US20210051020A1

    公开(公告)日：2021-02-18

    申请号：US16541009

    申请日：2019-08-14

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Chia-Jung CHEN ,  Chin-Hung CHANG ,  Kuen-Long CHANG

    IPC: H04L9/32 ,  G06F3/06

    Abstract: A memory device can comprise a memory, and an interface to receive a memory command sequence. A message authentication code MAC is provided with the command sequence. Control circuits on the device include a command decoder to decode a received a command sequence and to execute an identified memory operation. A message authentication engine includes logic to compute a value of a message authentication code to be matched with the received message authentication code based on the received command sequence and a stored key. The device can store a plurality of keys associated with one or more memory zones in the memory. Logic on the device prevents completion of the memory operation identified by the command sequence if the value computed does not match the received message authentication code.

    MEMORY CHIP HAVING SECURITY VERIFICATION FUNCTION AND MEMORY DEVICE
    6.
    发明申请
    MEMORY CHIP HAVING SECURITY VERIFICATION FUNCTION AND MEMORY DEVICE 审中-公开

    公开(公告)号：US20200242273A1

    公开(公告)日：2020-07-30

    申请号：US16726284

    申请日：2019-12-24

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Kuen-Long CHANG ,  Chia-Jung CHEN ,  Chin-Hung CHANG ,  Ken-Hui CHEN

    IPC: G06F21/72 ,  G06F12/1009 ,  G06F21/62

    Abstract: A memory chip comprises a first memory controller, a first data storage zone, a security unit and an address configuration unit. The first data storage zone is coupled to the first memory controller, and represented by a first physical address range. The security unit is coupled to the first memory controller. The address configuration unit is coupled to the first memory controller. The memory chip is configured to be coupled between a host controller and another memory chip. The another memory chip comprises a second data storage zone represented by a second physical address range. The address configuration unit records one or more relationships of a logical address range corresponding to the first physical address range and the second physical address range. The security unit is configured to encrypt and decrypt data in the first data storage zone and the second data storage zone.

    HIGH PERFORMANCE SECURE READ IN SECURE MEMORY
    8.
    发明公开
    HIGH PERFORMANCE SECURE READ IN SECURE MEMORY 审中-公开

    公开(公告)号：US20230315340A1

    公开(公告)日：2023-10-05

    申请号：US17824226

    申请日：2022-05-25

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Chia-Jung CHEN ,  Chin-Hung CHANG ,  Ken-Hui CHEN

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0622 ,  G06F3/0679

    Abstract: A memory device includes a command decoder that implements security logic to detect a command sequence to read a security region of a memory array with continuous encrypted data and to output/input specific contexts for the data. Output/input of specific contexts can be during a dummy cycle to achieve greater performance. A host interfacing can, for example, execute a single command to both get the encrypted data and specific contexts that were used to encrypt the data. Our technology can implement transferring data on the system bus in ciphertext and encrypted by a different Nonce or a different session key than used in a previous transfer operation. In this way, data will be represented with different ciphertext on the bus at different sessions; thereby defending against a replay attack.

    REFERENCE AND SENSING WITH BIT LINE STEPPING METHOD OF MEMORY
    10.
    发明申请
    REFERENCE AND SENSING WITH BIT LINE STEPPING METHOD OF MEMORY 有权
    参考和感测与位线步进方法的记忆

    公开(公告)号：US20140241070A1

    公开(公告)日：2014-08-28

    申请号：US13861970

    申请日：2013-04-12

    Applicant: Macronix International Co., Ltd.

    Inventor： Tien-Yen WANG ,  Chun-Hsiung HUNG ,  Chia-Jung CHEN

    IPC: G11C7/12 ,  G11C7/10

    CPC classification number: G11C13/004 ,  G11C7/02 ,  G11C7/12 ,  G11C7/14 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2013/0045 ,  G11C2013/0054

    Abstract: A sensing method for a memory is provided. The memory includes: a memory cell; a reference circuit generating a reference voltage and a clamp voltage; and a current supplying circuit receiving the clamp voltage to develop a cell current passing through the memory cell to form a cell voltage, wherein the cell voltage is used for incorporating with the reference voltage to determine the information stored in the memory.

    Abstract translation: 提供了一种用于存储器的感测方法。 存储器包括：存储器单元; 产生参考电压和钳位电压的参考电路; 以及电流供给电路，其接收所述钳位电压以开发通过所述存储单元的单元电流以形成单元电压，其中所述单元电压用于与参考电压结合以确定存储在所述存储器中的信息。

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