公开(公告)号：US11209985B2

公开(公告)日：2021-12-28

申请号：US16391439

申请日：2019-04-23

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Sheng-Lun Wu ,  Chun-Lien Su ,  Zong-Qi Zhou

IPC: G06F3/06 ,  G06F9/30 ,  G06F1/3206

Abstract: An input/output delay optimization method, used in an electronic system comprising a host controller and a memory device. The method comprising: switching the memory device from a first mode to a second mode a high power consumption mode of the memory device; transmitting one or more first read commands to the memory device, wherein the one or more first read commands are transmitted according to different output delay values; determining an optimized output delay value according to the response status of memory device for the one or more first read commands; transmitting one or more second read commands to the memory device, wherein the one or more second read commands are transmitted according to the optimized output delay value; receiving a known data from the memory device according to different input delay values; and determining an optimized input delay value according to the correctness of the received known data.

公开(公告)号：US08982636B2

公开(公告)日：2015-03-17

申请号：US13858134

申请日：2013-04-08

Applicant: Macronix International Co., Ltd.

Inventor： Tsung-Yi Chou ,  Ming-Feng Zhou ,  Chung-Yi Li ,  Zong-Qi Zhou

IPC: G11C11/4197 ,  G11C16/34 ,  G11C16/10 ,  G11C7/16 ,  G11C11/56

CPC classification number: G11C16/34 ,  G11C7/16 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2211/5634

Abstract: A memory comprises a memory cell, a sense amplifier, and a control unit. The memory cell stores a first bit and a second bit. The sense amplifier senses a first cell current and a second cell current corresponding to the first and the second bits respectively with a voltage applying on the memory cell. The control unit determines a digital state of the first bit by comparing a first reference current with the first cell current or by comparing a reference data with a first delta current between the first cell current and the second cell current.

Abstract translation: 存储器包括存储单元，读出放大器和控制单元。 存储单元存储第一位和第二位。 感测放大器以施加在存储器单元上的电压分别感测对应于第一和第二位的第一单元电流和第二单元电流。 控制单元通过将第一参考电流与第一单元电流进行比较来确定第一位的数字状态，或者通过将参考数据与第一单元电流和第二单元电流之间的第一增量电流进行比较来确定第一位的数字状态。

公开(公告)号：US20130194866A1

公开(公告)日：2013-08-01

申请号：US13858134

申请日：2013-04-08

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Tsung-Yi Chou ,  Ming-Feng Zhou ,  Chung-Yi Li ,  Zong-Qi Zhou

IPC: G11C16/34

CPC classification number: G11C16/34 ,  G11C7/16 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2211/5634

Abstract: A memory comprises a memory cell, a sense amplifier, and a control unit. The memory cell stores a first bit and a second bit. The sense amplifier senses a first cell current and a second cell current corresponding to the first and the second bits respectively with a voltage applying on the memory cell. The control unit determines a digital state of the first bit by comparing a first reference current with the first cell current or by comparing a reference data with a first delta current between the first cell current and the second cell current.

Abstract translation: 存储器包括存储单元，读出放大器和控制单元。 存储单元存储第一位和第二位。 感测放大器以施加在存储器单元上的电压分别感测对应于第一和第二位的第一单元电流和第二单元电流。 控制单元通过将第一参考电流与第一单元电流进行比较来确定第一位的数字状态，或者通过将参考数据与第一单元电流和第二单元电流之间的第一增量电流进行比较来确定第一位的数字状态。