Multi-stage interconnect network in a parallel processing network device
    2.
    发明授权
    Multi-stage interconnect network in a parallel processing network device 有权
    并行处理网络设备中的多级互联网络

    公开(公告)号:US09571380B2

    公开(公告)日:2017-02-14

    申请号:US14482980

    申请日:2014-09-10

    Abstract: A packet is received at a packet processing element, among a plurality of like packet processing elements, of a network device, and request specifying a processing operation to be performed with respect to the packet by an accelerator engine functionally different from the plurality of like packet processing elements is generated by the packet processing element. The request is transmitted to an interconnect network that includes a plurality of interconnect units arranged in stages. A path through the interconnect network is selected among a plurality of candidate paths, wherein no path of the candidate paths includes multiple interconnect units within a same stage of the interconnect network. The request is then transmitted via the determined path to a particular accelerator engine among multiple candidate accelerator engines configured to perform the processing operation. The processing operation is then performed by the particular accelerator engine.

    Abstract translation: 在网络设备的多个相似的分组处理单元中的分组处理元件处接收分组,并且通过与多个相似分组功能不同的加速器引擎来指定要对该分组执行的处理操作的请求 处理元件由分组处理元件生成。 该请求被发送到包括分阶段布置的多个互连单元的互连网络。 在多个候选路径中选择通过互连网络的路径,其中候选路径的路径不包括在互连网络的相同阶段内的多个互连单元。 然后,该请求经由确定的路径被发送到配置成执行处理操作的多个候选加速器引擎中的特定加速器引擎。 然后由特定加速器引擎执行处理操作。

Patent Agency Ranking