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1.发明授权Frequency synthesizer with injection pulling/pushing suppression/mitigation and related frequency synthesizing method thereof 有权具有注入拉/推抑制/抑制的频率合成器及其相关频率合成方法公开(公告)号：US09473157B2
公开(公告)日：2016-10-18
申请号：US14339459
申请日：2014-07-24
Applicant: MEDIATEK INC.
Inventor： Chun-Ming Kuo , Chii-Horng Chen , Shih-Chi Shen , Ai-Hsuan Liu
CPC classification number: H03L7/16 , G04F10/005 , H03L7/099 , H03L7/1075 , H03L2207/50
Abstract: A frequency synthesizer includes a phase-locked loop (PLL) and a loop bandwidth controller. The PLL generates an output clock according to a reference clock. The loop bandwidth controller checks at least one indicator indicative of injection pulling/pushing of the PLL to configure a loop bandwidth of the PLL. In one exemplary design, the loop bandwidth controller sets the loop bandwidth of the PLL by controlling a configuration of a loop filter included in the PLL. For example, the PLL is an all-digital phase-locked loop (ADPLL), and the loop filter is a digital loop filter of the ADPLL.
Abstract translation: 频率合成器包括锁相环（PLL）和环路带宽控制器。 PLL根据参考时钟产生输出时钟。 环路带宽控制器检查至少一个指示PLL的注入拉/推的指示器，以配置PLL的环路带宽。 在一个示例性设计中，环路带宽控制器通过控制PLL中包括的环路滤波器的配置来设置PLL的环路带宽。 例如，PLL是全数字锁相环（ADPLL），环路滤波器是ADPLL的数字环路滤波器。
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2.发明申请FREQUENCY SYNTHESIZER WITH INJECTION PULLING/PUSHING SUPPRESSION/MITIGATION AND RELATED FREQUENCY SYNTHESIZING METHOD THEREOF 有权具有注射拉伸/推压抑制/缓解的频率合成器及其相关的频率合成方法公开(公告)号：US20160028411A1
公开(公告)日：2016-01-28
申请号：US14339459
申请日：2014-07-24
Applicant: MEDIATEK INC.
Inventor： Chun-Ming Kuo , Chii-Horng Chen , Shih-Chi Shen , Ai-Hsuan Liu
CPC classification number: H03L7/16 , G04F10/005 , H03L7/099 , H03L7/1075 , H03L2207/50
Abstract: A frequency synthesizer includes a phase-locked loop (PLL) and a loop bandwidth controller. The PLL generates an output clock according to a reference clock. The loop bandwidth controller checks at least one indicator indicative of injection pulling/pushing of the PLL to configure a loop bandwidth of the PLL. In one exemplary design, the loop bandwidth controller sets the loop bandwidth of the PLL by controlling a configuration of a loop filter included in the PLL. For example, the PLL is an all-digital phase-locked loop (ADPLL), and the loop filter is a digital loop filter of the ADPLL.
Abstract translation: 频率合成器包括锁相环（PLL）和环路带宽控制器。 PLL根据参考时钟产生输出时钟。 环路带宽控制器检查至少一个指示PLL的注入拉/推的指示器，以配置PLL的环路带宽。 在一个示例性设计中，环路带宽控制器通过控制PLL中包括的环路滤波器的配置来设置PLL的环路带宽。 例如，PLL是全数字锁相环（ADPLL），环路滤波器是ADPLL的数字环路滤波器。
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