公开(公告)号：US20240276255A1

公开(公告)日：2024-08-15

申请号：US18110351

申请日：2023-02-15

Applicant: MEDIATEK INC.

Inventor： Chii-Horng Chen ,  Shih-Chi Shen ,  Yen-Hui Yeh ,  Ping-Hung Chiang

IPC: H04W24/08

CPC classification number: H04W24/08

Abstract: A method for handling radio link monitoring (RLM) includes: receiving downlink (DL) data from a network device; performing a first measurement according to the DL data, to generate a first measurement result of the DL data; comparing the first measurement result and a first threshold, to determine a first indication; comparing the first measurement result and a second threshold, to determine a second indication; and determining whether a radio link failure (RLF) occurs according to at least one of the first indication and the second indication.

公开(公告)号：US09473157B2

公开(公告)日：2016-10-18

申请号：US14339459

申请日：2014-07-24

Applicant: MEDIATEK INC.

Inventor： Chun-Ming Kuo ,  Chii-Horng Chen ,  Shih-Chi Shen ,  Ai-Hsuan Liu

IPC: H03L7/16 ,  G04F10/00 ,  H03L7/099 ,  H03L7/107

CPC classification number: H03L7/16 ,  G04F10/005 ,  H03L7/099 ,  H03L7/1075 ,  H03L2207/50

Abstract: A frequency synthesizer includes a phase-locked loop (PLL) and a loop bandwidth controller. The PLL generates an output clock according to a reference clock. The loop bandwidth controller checks at least one indicator indicative of injection pulling/pushing of the PLL to configure a loop bandwidth of the PLL. In one exemplary design, the loop bandwidth controller sets the loop bandwidth of the PLL by controlling a configuration of a loop filter included in the PLL. For example, the PLL is an all-digital phase-locked loop (ADPLL), and the loop filter is a digital loop filter of the ADPLL.

Abstract translation: 频率合成器包括锁相环（PLL）和环路带宽控制器。 PLL根据参考时钟产生输出时钟。 环路带宽控制器检查至少一个指示PLL的注入拉/推的指示器，以配置PLL的环路带宽。 在一个示例性设计中，环路带宽控制器通过控制PLL中包括的环路滤波器的配置来设置PLL的环路带宽。 例如，PLL是全数字锁相环（ADPLL），环路滤波器是ADPLL的数字环路滤波器。

公开(公告)号：US09300305B1

公开(公告)日：2016-03-29

申请号：US14557462

申请日：2014-12-02

Applicant: MEDIATEK INC.

Inventor： Chun-Ming Kuo ,  Chii-Horng Chen ,  Shih-Chi Shen

IPC: H03L7/099 ,  H03M3/00

CPC classification number: H03L7/0991 ,  H03L7/0802 ,  H03L7/093 ,  H03L7/16 ,  H03L2207/06 ,  H03L2207/50 ,  H03M3/30

Abstract: A frequency synthesizer includes a digitally controlled oscillator, a sigma-delta modulation circuit and a controller. The digitally controlled oscillator is arranged to generate an oscillating clock. The sigma-delta modulation circuit is arranged to generate an SDM input to the digitally controlled oscillator. The controller is arranged to adjust an operating frequency of the SDM circuit in response to a transmit power level of a transmitter using the oscillating clock.

Abstract translation: 频率合成器包括数字控制振荡器，Σ-Δ调制电路和控制器。 数字控制振荡器被布置成产生振荡时钟。 Σ-Δ调制电路被布置成产生到数字控制振荡器的SDM输入。 控制器被布置成响应于使用振荡时钟的发射机的发射功率电平来调整SDM电路的工作频率。

公开(公告)号：US20160028411A1

公开(公告)日：2016-01-28

申请号：US14339459

申请日：2014-07-24

Applicant: MEDIATEK INC.

Inventor： Chun-Ming Kuo ,  Chii-Horng Chen ,  Shih-Chi Shen ,  Ai-Hsuan Liu

IPC: H03L7/16 ,  H03L7/099 ,  G04F10/00

CPC classification number: H03L7/16 ,  G04F10/005 ,  H03L7/099 ,  H03L7/1075 ,  H03L2207/50

Abstract: A frequency synthesizer includes a phase-locked loop (PLL) and a loop bandwidth controller. The PLL generates an output clock according to a reference clock. The loop bandwidth controller checks at least one indicator indicative of injection pulling/pushing of the PLL to configure a loop bandwidth of the PLL. In one exemplary design, the loop bandwidth controller sets the loop bandwidth of the PLL by controlling a configuration of a loop filter included in the PLL. For example, the PLL is an all-digital phase-locked loop (ADPLL), and the loop filter is a digital loop filter of the ADPLL.

Abstract translation: 频率合成器包括锁相环（PLL）和环路带宽控制器。 PLL根据参考时钟产生输出时钟。 环路带宽控制器检查至少一个指示PLL的注入拉/推的指示器，以配置PLL的环路带宽。 在一个示例性设计中，环路带宽控制器通过控制PLL中包括的环路滤波器的配置来设置PLL的环路带宽。 例如，PLL是全数字锁相环（ADPLL），环路滤波器是ADPLL的数字环路滤波器。