公开(公告)号：US10886958B2

公开(公告)日：2021-01-05

申请号：US16820925

申请日：2020-03-17

Applicant: MEDIATEK INC.

Inventor： Pei-Kai Liao ,  Chun-Ming Kuo ,  Chien-Hwa Hwang ,  Jiann-Ching Guey

IPC: H04B1/12 ,  H04W72/04

Abstract: A method of providing over-the-air assistance information for interference cancellation or suppression to the receiver is proposed. Under a first solution, a two-stage DCI (downlink control information) or SCI (sidelink control information) scheduling method is proposed. The set of first-stage DCI or SCI provides a part of scheduling information which is beneficial for interference cancellation or suppression and is broadcasted by a transmitter or scheduler to all receivers. The set of second-stage DCI or SCI includes the remaining scheduling information and is unicasted by a transmitter or scheduler to each receiver. Under a second solution, assistance information DCI for interference cancellation or suppression is broadcasted by a transmitter or scheduler to all receivers.

公开(公告)号：US20210083704A1

公开(公告)日：2021-03-18

申请号：US17108138

申请日：2020-12-01

Applicant: MEDIATEK INC.

Inventor： Pei-Kai Liao ,  Chun-Ming Kuo ,  Chien-Hwa Hwang ,  Jiann-Ching Guey

IPC: H04B1/12 ,  H04W72/04

Abstract: A method of providing over-the-air assistance information for interference cancellation or suppression to the receiver is proposed. Under a first solution, a two-stage DCI (downlink control information) or SCI (sidelink control information) scheduling method is proposed. The set of first-stage DCI or SCI provides a part of scheduling information which is beneficial for interference cancellation or suppression and is broadcasted by a transmitter or scheduler to all receivers. The set of second-stage DCI or SCI includes the remaining scheduling information and is unicasted by a transmitter or scheduler to each receiver. Under a second solution, assistance information DCI for interference cancellation or suppression is broadcasted by a transmitter or scheduler to all receivers.

公开(公告)号：US09867135B1

公开(公告)日：2018-01-09

申请号：US15425183

申请日：2017-02-06

Applicant: MEDIATEK INC.

Inventor： Shao-Wei Feng ,  Shih-Chi Shen ,  Tso-Mo Chen ,  Chun-Ming Kuo

IPC: H03L7/26 ,  H04W52/02 ,  H03L7/16 ,  H03B5/32

CPC classification number: H04W52/029 ,  G06F7/68 ,  H03K5/00006 ,  H03L7/16 ,  H04W52/0287 ,  Y02D70/00

Abstract: A frequency-generating circuit includes a frequency synthesizer circuit and a reference clock signal processor. The frequency synthesizer circuit receives a processed reference clock signal and generates a radio-frequency clock signal according to the processed reference clock signal. The reference clock signal processor receives an original reference clock signal from an oscillator and processes the original reference clock signal according to an indication signal to generate the processed reference clock signal. The indication signal is generated according to a required reference clock frequency of a communications apparatus. When the required reference clock frequency is high, a frequency of the processed reference clock signal is a multiple of a frequency of the original reference clock signal, and when the required reference clock frequency is low, the frequency of the original reference clock signal is a multiple of the frequency of the processed reference clock signal.

公开(公告)号：US20240224254A1

公开(公告)日：2024-07-04

申请号：US18092969

申请日：2023-01-04

Applicant: MEDIATEK INC.

Inventor： Sheng-Hua Yang ,  Yen-Ping Lin ,  Shih-Chi Shen ,  Chun-Ming Kuo ,  Yen-Hui Yeh ,  Ping-Hung Chiang

IPC: H04W72/044 ,  H04L5/00 ,  H04W72/54

CPC classification number: H04W72/0466 ,  H04L5/0051 ,  H04W72/54

Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a UE. The configuration specifies a bundle size N. Modulation symbols in N consecutive PRBs are precoded with a same precoder. The UE determines whether a precoding condition is true. The precoding condition is that modulation symbols in a first set of resources and a second set of resources are precoded with a same precoder. Each set of the first set of resources and the second set of resources contains N PRBs. When the precoding condition is met: the UE measures reference signals in the second set of resources; the UE determines a channel condition of the first set of resources in consideration of the measurements of the reference signals in the second set of resources.

公开(公告)号：US20200304159A1

公开(公告)日：2020-09-24

申请号：US16820925

申请日：2020-03-17

Applicant: MEDIATEK INC.

Inventor： Pei-Kai Liao ,  Chun-Ming Kuo ,  Chien-Hwa Hwang ,  Jiann-Ching Guey

IPC: H04B1/12 ,  H04W72/04

Abstract: A method of providing over-the-air assistance information for interference cancellation or suppression to the receiver is proposed. Under a first solution, a two-stage DCI (downlink control information) or SCI (sidelink control information) scheduling method is proposed. The set of first-stage DCI or SCI provides a part of scheduling information which is beneficial for interference cancellation or suppression and is broadcasted by a transmitter or scheduler to all receivers. The set of second-stage DCI or SCI includes the remaining scheduling information and is unicasted by a transmitter or scheduler to each receiver. Under a second solution, assistance information DCI for interference cancellation or suppression is broadcasted by a transmitter or scheduler to all receivers.

公开(公告)号：US20160028411A1

公开(公告)日：2016-01-28

申请号：US14339459

申请日：2014-07-24

Applicant: MEDIATEK INC.

Inventor： Chun-Ming Kuo ,  Chii-Horng Chen ,  Shih-Chi Shen ,  Ai-Hsuan Liu

IPC: H03L7/16 ,  H03L7/099 ,  G04F10/00

CPC classification number: H03L7/16 ,  G04F10/005 ,  H03L7/099 ,  H03L7/1075 ,  H03L2207/50

Abstract: A frequency synthesizer includes a phase-locked loop (PLL) and a loop bandwidth controller. The PLL generates an output clock according to a reference clock. The loop bandwidth controller checks at least one indicator indicative of injection pulling/pushing of the PLL to configure a loop bandwidth of the PLL. In one exemplary design, the loop bandwidth controller sets the loop bandwidth of the PLL by controlling a configuration of a loop filter included in the PLL. For example, the PLL is an all-digital phase-locked loop (ADPLL), and the loop filter is a digital loop filter of the ADPLL.

Abstract translation: 频率合成器包括锁相环（PLL）和环路带宽控制器。 PLL根据参考时钟产生输出时钟。 环路带宽控制器检查至少一个指示PLL的注入拉/推的指示器，以配置PLL的环路带宽。 在一个示例性设计中，环路带宽控制器通过控制PLL中包括的环路滤波器的配置来设置PLL的环路带宽。 例如，PLL是全数字锁相环（ADPLL），环路滤波器是ADPLL的数字环路滤波器。

公开(公告)号：US09966986B1

公开(公告)日：2018-05-08

申请号：US15389708

申请日：2016-12-23

Applicant: MEDIATEK INC.

Inventor： Shih-Chi Shen ,  Shao-Wei Feng ,  Chun-Ming Kuo ,  Chi-Hsueh Wang ,  Ang-Sheng Lin

IPC: H04B1/18 ,  H04B1/40 ,  H04W52/02

CPC classification number: H04B1/40 ,  H03L7/0994 ,  H03L7/18 ,  H03L2207/50 ,  H04W52/02 ,  H04W52/0216 ,  H04W52/0235 ,  H04W52/0274 ,  H04W52/0287

Abstract: A frequency-generating circuit includes a frequency synthesizer circuit and a controller. The frequency synthesizer circuit generates a radio-frequency clock signal according to a reference clock signal and a channel number. The controller is coupled to the frequency synthesizer circuit, generates a power-down control signal for controlling at least a portion of the frequency synthesizer circuit to power down. The frequency synthesizer circuit includes an accumulator for generating an accumulated value according to the channel number. The frequency synthesizer circuit generates the radio-frequency clock signal according to the reference clock signal and the accumulated value. The controller maintains the accumulated value of the accumulator when the portion of the frequency synthesizer circuit powers down.

公开(公告)号：US09473157B2

公开(公告)日：2016-10-18

申请号：US14339459

申请日：2014-07-24

Applicant: MEDIATEK INC.

Inventor： Chun-Ming Kuo ,  Chii-Horng Chen ,  Shih-Chi Shen ,  Ai-Hsuan Liu

IPC: H03L7/16 ,  G04F10/00 ,  H03L7/099 ,  H03L7/107

CPC classification number: H03L7/16 ,  G04F10/005 ,  H03L7/099 ,  H03L7/1075 ,  H03L2207/50

Abstract: A frequency synthesizer includes a phase-locked loop (PLL) and a loop bandwidth controller. The PLL generates an output clock according to a reference clock. The loop bandwidth controller checks at least one indicator indicative of injection pulling/pushing of the PLL to configure a loop bandwidth of the PLL. In one exemplary design, the loop bandwidth controller sets the loop bandwidth of the PLL by controlling a configuration of a loop filter included in the PLL. For example, the PLL is an all-digital phase-locked loop (ADPLL), and the loop filter is a digital loop filter of the ADPLL.

Abstract translation: 频率合成器包括锁相环（PLL）和环路带宽控制器。 PLL根据参考时钟产生输出时钟。 环路带宽控制器检查至少一个指示PLL的注入拉/推的指示器，以配置PLL的环路带宽。 在一个示例性设计中，环路带宽控制器通过控制PLL中包括的环路滤波器的配置来设置PLL的环路带宽。 例如，PLL是全数字锁相环（ADPLL），环路滤波器是ADPLL的数字环路滤波器。

公开(公告)号：US09300305B1

公开(公告)日：2016-03-29

申请号：US14557462

申请日：2014-12-02

Applicant: MEDIATEK INC.

Inventor： Chun-Ming Kuo ,  Chii-Horng Chen ,  Shih-Chi Shen

IPC: H03L7/099 ,  H03M3/00

CPC classification number: H03L7/0991 ,  H03L7/0802 ,  H03L7/093 ,  H03L7/16 ,  H03L2207/06 ,  H03L2207/50 ,  H03M3/30

Abstract: A frequency synthesizer includes a digitally controlled oscillator, a sigma-delta modulation circuit and a controller. The digitally controlled oscillator is arranged to generate an oscillating clock. The sigma-delta modulation circuit is arranged to generate an SDM input to the digitally controlled oscillator. The controller is arranged to adjust an operating frequency of the SDM circuit in response to a transmit power level of a transmitter using the oscillating clock.

Abstract translation: 频率合成器包括数字控制振荡器，Σ-Δ调制电路和控制器。 数字控制振荡器被布置成产生振荡时钟。 Σ-Δ调制电路被布置成产生到数字控制振荡器的SDM输入。 控制器被布置成响应于使用振荡时钟的发射机的发射功率电平来调整SDM电路的工作频率。

公开(公告)号：US20140038538A1

公开(公告)日：2014-02-06

申请号：US13927098

申请日：2013-06-25

Applicant: MEDIATEK INC.

Inventor： Chun-Ming Kuo ,  Shih-Chi Shen

IPC: H04B1/16

CPC classification number: H04B1/16 ,  H04B1/0007 ,  H04B1/1615 ,  H04L27/0006 ,  H04L27/28 ,  H04W52/0229 ,  Y02D70/40

Abstract: An embodiment of the invention provides a method of processing a radio frequency (RF) signal. According to the embodiment, the RF signal is first synthesized with a synthesis signal to generate a synthesized signal. Then, the synthesized signal is filtered with a filtering bandwidth to generate a filtered signal. Next, the filtered signal is converted into digital data. Then, the digital data is processed to analyze a plurality of carriers within the filtering bandwidth as presented in the RF signal.

Abstract translation: 本发明的实施例提供一种处理射频（RF）信号的方法。 根据实施例，RF信号首先用合成信号合成以产生合成信号。 然后，用滤波带宽对合成信号进行滤波，生成滤波信号。 接下来，滤波后的信号被转换为数字数据。 然后，处理数字数据以分析在RF信号中呈现的过滤带宽内的多个载波。