公开(公告)号：US20220343053A1

公开(公告)日：2022-10-27

申请号：US17708438

申请日：2022-03-30

Applicant: MEDIATEK INC.

Inventor： Kin-Hooi DIA ,  Ho-Chieh HSIEH

IPC: G06F30/398 ,  G06F30/3312 ,  G06F30/392 ,  H01L27/092

Abstract: Semiconductor structures are provided. A semiconductor structure includes a cell array. The cell array includes a first regular cell, a second regular cell and a first mixed cell. Each P-type transistor has a first threshold voltage and each N-type transistor has a second threshold voltage in the first regular cell. Each P-type transistor has a third threshold voltage and each N-type transistor has a fourth threshold voltage in the second regular cell. Each P-type transistor has the first threshold voltage and each N-type transistor has the fourth threshold voltage in the first mixed cell. The first regular cell, the second regular cell and the first mixed cell are arranged in the same row of the cell array. The first mixed cell is arranged between the first and second regular cells and is in contact with the first regular cell.

公开(公告)号：US20250151391A1

公开(公告)日：2025-05-08

申请号：US19009302

申请日：2025-01-03

Applicant: MEDIATEK INC.

Inventor： Kin-Hooi DIA ,  Ho-Chieh HSIEH

IPC: H10D84/90

Abstract: A semiconductor structure is provided. A logic cell with a logic function includes P-type and N-type transistors in first and second active regions over a semiconductor substrate, first and a second isolation structures on opposite edges of the first and second active regions, first and third transistors in the first and second active regions and between the first isolation structure and the P-type transistors, second and fourth transistors in the first and second active region and between the second isolation structure and the P-type transistors. Each of the N-type transistors and a respective P-type transistor shares a first gate electrode along the first direction. The first and third transistors share a second gate electrode extending along the first direction. The second and fourth transistors share a third gate electrode extending along the first direction. The P-type transistors and the N-type transistors are configured to perform the logic function.

公开(公告)号：US20230178557A1

公开(公告)日：2023-06-08

申请号：US18050630

申请日：2022-10-28

Applicant: MEDIATEK INC.

Inventor： Ho-Chieh HSIEH ,  Kin-Hooi DIA ,  Hsing-I TSAI

IPC: H01L27/118 ,  H01L27/02

CPC classification number: H01L27/11807 ,  H01L27/0207 ,  H01L2027/11829 ,  H01L2027/11881

Abstract: A semiconductor structure is provided. A logic cell includes a first transistor in a first active region, a second gate electrode and a third gate electrode on opposite sides of the first transistor, a second transistor in a second active region, and a first isolation structure and a second isolation structure on opposite edges of the second active region. The first transistor includes a first gate electrode extending in a first direction. The second and third gate electrodes extend in the first direction, and the first and second isolation structures extend in the first direction. The second transistor and the first transistor share the first gate electrode. The first isolation structure is aligned with the second gate structure in the first direction, and the second isolation structure is aligned with the third gate structure in the first direction.

公开(公告)号：US20230178537A1

公开(公告)日：2023-06-08

申请号：US18051026

申请日：2022-10-31

Applicant: MEDIATEK INC.

Inventor： Kin-Hooi DIA ,  Ho-Chieh HSIEH ,  Hsing-I TSAI

IPC: H01L27/02 ,  H01L27/092

CPC classification number: H01L27/0207 ,  H01L27/092 ,  H01L21/76224

Abstract: A semiconductor structure is provided. The semiconductor structure includes a cell array having a plurality of rows. The cell array includes a plurality of first logic cells arranged in at least one first row, and a plurality of second logic cells arranged in at least one second row. The first logic cells share a first active region. Each of the second logic cells has a second active region, and the second active regions of two adjacent second logic cells are separated from each other by an isolation structure. The first logic cells of the first row are in contact with the second logic cells of the second row.

公开(公告)号：US20220223623A1

公开(公告)日：2022-07-14

申请号：US17535760

申请日：2021-11-26

Applicant: MEDIATEK INC.

Inventor： Kin-Hooi DIA ,  Ho-Chieh HSIEH

IPC: H01L27/118

Abstract: A semiconductor structure is provided. A logic cell with a logic function includes a plurality of first transistors in an active region over a semiconductor substrate, a second transistor in the active region, a third transistor in the active region, and first and second isolation structures on opposite edges of the active region and extending along the first direction. Each first transistor includes a first gate electrode extending along the first direction. The second transistor includes a second gate electrode extending along the first direction. The third transistor includes a third gate electrode extending along the first direction. The first gate electrodes are disposed between the first and second isolation structures. The second gate electrode is disposed between the first gate electrodes and the first isolation structure. The third gate electrode is disposed between the first gate electrodes and the second isolation structure.

公开(公告)号：US20230179206A1

公开(公告)日：2023-06-08

申请号：US18054032

申请日：2022-11-09

Applicant: MEDIATEK INC.

Inventor： Kin-Hooi DIA ,  Ssu-Yen WU ,  Shih-Yun LIN

IPC: H03K19/00

CPC classification number: H03K19/0016

Abstract: A clock gating cell is provided. The clock gating cell includes an input stage and an output stage. The input stage receives a first clock signal and at least one input enable signal and generates a first enable signal corresponding to one of the least one input enable signal according to the first clock signal. The output stage is coupled to the input stage. The output stage receives the first enable signal and the first clock signal and generates a clock gating signal according to the first enable signal and the first clock signal. The input stage operates based on a first voltage threshold, and the output stage operates based on a second voltage threshold. The first voltage threshold is different from the second voltage threshold.

公开(公告)号：US20170018572A1

公开(公告)日：2017-01-19

申请号：US15168507

申请日：2016-05-31

Applicant: MediaTek Inc.

Inventor： Kin-Hooi DIA ,  Hugh Thomas Mair ,  Shao-Hua Huang ,  Wen-Yi Lin

IPC: H01L27/118 ,  H01L49/02 ,  H01L27/02 ,  H01L27/06

CPC classification number: H01L27/0629 ,  H03K19/00361 ,  H03K19/00369

Abstract: A standard cell circuit includes a standard cell unit and a first resistive device. The standard cell unit is coupled to at least one resistor. The first resistive device is coupled to the standard cell unit and provides a first current path for a first current to flow through.

Abstract translation: 标准单元电路包括标准单元单元和第一电阻设备。 标准单元单元耦合到至少一个电阻器。 第一电阻器件耦合到标准单元单元并且提供用于第一电流流过的第一电流路径。