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公开(公告)号：US20160320821A1
公开(公告)日：2016-11-03
申请号：US15138462
申请日：2016-04-26
Applicant: MediaTek Inc.
Inventor： Hugh Thomas Mair , Yi-Te Chiu , Che-Wei Wu , Lee-Kee Yong , Chia-Wei Wang , Cheng-Hsing Chien , Uming Ko
IPC: G06F1/28
CPC classification number: G06F1/3296 , G06F1/3275 , Y02D10/14 , Y02D10/172
Abstract: A processing device performs dual-rail power equalization for its memory cell array and logic circuitry. The memory cell array is coupled to a first power rail through a first switch to receive a first voltage level. The logic circuitry is coupled to a second power rail through a second switch to receive a second voltage level that is different from the first voltage level. The processing device also includes a power switch coupled to at least the second power rail and operative to be enabled to equalize voltage supplied to the memory cell array and the logic circuitry.
Abstract translation: 处理装置为其存储单元阵列和逻辑电路执行双轨功率均衡。 存储单元阵列通过第一开关耦合到第一电源轨，以接收第一电压电平。 逻辑电路通过第二开关耦合到第二电源轨，以接收不同于第一电压电平的第二电压电平。 处理装置还包括耦合到至少第二电力轨的功率开关，并且被操作以使得能够均衡提供给存储单元阵列和逻辑电路的电压。
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Patent Agency Ranking
公开(公告)号：US10345882B2
公开(公告)日：2019-07-09
申请号：US14933542
申请日：2015-11-05
Applicant: MEDIATEK INC.
Inventor： Huajun Wen , Hugh Thomas Mair , Hsin-Chen Chen , Brian King Flachs
IPC: G06F1/3203 , G06F1/04
Abstract: A dynamic power meter circuit receives a set of clock signals. The clock signals are summed by a clock sum adder, thereby generating a clock sum value. A dynamic power meter output value is generated based at least in part on the clock sum value. In one particular example, a dynamic power meter circuit receives clock signals and from them generates a clock sum model sub-value. The dynamic power meter circuit also receives event signals, and from them generates an architectural event model sub-value. A corresponding pair of clock sum model sub-value and architectural event model sub-value are then ratiometrically combined, thereby generating a dynamic power meter output value. Due to the use of both event signals and clock signals, a stream of dynamic power meter output values is generated that more closely tracks actual dynamic power of a circuit being monitored.
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公开(公告)号：US10361190B2
公开(公告)日：2019-07-23
申请号：US15168507
申请日：2016-05-31
Applicant: MediaTek Inc.
Inventor： Kin-Hooi Dia , Hugh Thomas Mair , Shao-Hua Huang , Wen-Yi Lin
IPC: H03K19/017 , H01L27/06 , H03K19/003
Abstract: A standard cell circuit includes a standard cell unit and a first resistive device. The standard cell unit is coupled to at least one resistor. The first resistive device is coupled to the standard cell unit and provides a first current path for a first current to flow through.
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公开(公告)号：US09690365B2
公开(公告)日：2017-06-27
申请号：US15138462
申请日：2016-04-26
Applicant: MediaTek Inc.
Inventor： Hugh Thomas Mair , Yi-Te Chiu , Che-Wei Wu , Lee-Kee Yong , Chia-Wei Wang , Cheng-Hsing Chien , Uming Ko
CPC classification number: G06F1/3296 , G06F1/3275 , Y02D10/14 , Y02D10/172
Abstract: A processing device performs dual-rail power equalization for its memory cell array and logic circuitry. The memory cell array is coupled to a first power rail through a first switch to receive a first voltage level. The logic circuitry is coupled to a second power rail through a second switch to receive a second voltage level that is different from the first voltage level. The processing device also includes a power switch coupled to at least the second power rail and operative to be enabled to equalize voltage supplied to the memory cell array and the logic circuitry.
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5.发明申请公开(公告)号：US20160291068A1
公开(公告)日：2016-10-06
申请号：US14933542
申请日：2015-11-05
Applicant: MEDIATEK INC.
Inventor： Huajun Wen , Hugh Thomas Mair , Hsin-Chen Chen , Brian King Flachs
CPC classification number: G06F1/3203 , G06F1/04
Abstract: A dynamic power meter circuit receives a set of clock signals. The clock signals are summed by a clock sum adder, thereby generating a clock sum value. A dynamic power meter output value is generated based at least in part on the clock sum value. In one particular example, a dynamic power meter circuit receives clock signals and from them generates a clock sum model sub-value. The dynamic power meter circuit also receives event signals, and from them generates an architectural event model sub-value. A corresponding pair of clock sum model sub-value and architectural event model sub-value are then ratiometrically combined, thereby generating a dynamic power meter output value. Due to the use of both event signals and clock signals, a stream of dynamic power meter output values is generated that more closely tracks actual dynamic power of a circuit being monitored.
Abstract translation: 动态功率计电路接收一组时钟信号。 时钟信号由时钟和加法器相加，从而产生时钟和值。 至少部分地基于时钟和值产生动态功率计输出值。 在一个具体示例中，动态功率计电路接收时钟信号，并从中产生时钟和模型子值。 动态功率计电路还接收事件信号，并从它们生成建筑事件模型子值。 然后将对应的一对时钟和模型子值和架构事件模型子值进行比例组合，从而生成动态功率计输出值。 由于使用了事件信号和时钟信号两者，所以产生动态功率计输出值流，其更紧密地跟踪被监控电路的实际动态功率。
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公开(公告)号：US20170018572A1
公开(公告)日：2017-01-19
申请号：US15168507
申请日：2016-05-31
Applicant: MediaTek Inc.
Inventor： Kin-Hooi DIA , Hugh Thomas Mair , Shao-Hua Huang , Wen-Yi Lin
IPC: H01L27/118 , H01L49/02 , H01L27/02 , H01L27/06
CPC classification number: H01L27/0629 , H03K19/00361 , H03K19/00369
Abstract: A standard cell circuit includes a standard cell unit and a first resistive device. The standard cell unit is coupled to at least one resistor. The first resistive device is coupled to the standard cell unit and provides a first current path for a first current to flow through.
Abstract translation: 标准单元电路包括标准单元单元和第一电阻设备。 标准单元单元耦合到至少一个电阻器。 第一电阻器件耦合到标准单元单元并且提供用于第一电流流过的第一电流路径。
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