公开(公告)号：US20220366116A1

公开(公告)日：2022-11-17

申请号：US17673755

申请日：2022-02-16

Applicant: MEDIATEK INC.

Inventor： Yu-Tung Chang ,  Yi-Chun Tsai ,  Tung-Kai Tsai ,  Yi-Te Chiu ,  Shih-Yun Lin ,  Hung-Ming Chu ,  Yi-Feng Chen

IPC: G06F30/392

Abstract: An integrated circuit (IC) may include a plurality of functional blocks, and each functional block of the plurality of functional blocks may include hardware circuits, wherein the plurality of functional blocks may include a first functional block. In addition, the first functional block may include a first macro circuit that is positioned within a first sub-region of the first functional block, wherein among multiple sides of the first sub-region, a first side of the first sub-region is closest to a boundary of the first functional block. Additionally, a first intermediate sub-region of the first functional block is positioned between the first side of the first sub-region and the boundary of the first functional block, and there is no tap cell in the first intermediate sub-region of the first functional block.

公开(公告)号：US10067000B2

公开(公告)日：2018-09-04

申请号：US14855592

申请日：2015-09-16

Applicant: MediaTek Inc.

Inventor： Bo-Jr Huang ,  Yi-Feng Chen ,  Jia-Wei Fang

IPC: G01K7/01 ,  G01K7/00 ,  H03K3/03

Abstract: The invention provides an inverter. The inverter includes a first converter and a second converter. The first converter is coupled between a supply voltage and an output node of the inverter. The second converter is coupled between the output node of the inverter and a ground voltage. The first converter, the second converter, or both include diode-connected transistors. The propagation delay time of the inverter is substantially a linear function of the temperature of the inverter.

公开(公告)号：US10776550B1

公开(公告)日：2020-09-15

申请号：US16383650

申请日：2019-04-14

Applicant: MEDIATEK INC.

Inventor： Yi-Feng Chen ,  Chun-Sung Su

IPC: H03K5/13 ,  G06F30/39

Abstract: An integrated circuit includes a path logic and a timing fixing circuit. The path logic is coupled between an output pin of a first circuit and an input pin of a second circuit. The timing fixing circuit has an input pin coupled to the path logic, and is used to adjust a propagation delay of the path logic. The timing fixing circuit introduces no short-circuit current under normal operation.

公开(公告)号：US10027316B2

公开(公告)日：2018-07-17

申请号：US15243237

申请日：2016-08-22

Applicant: MediaTek Inc.

Inventor： Yi-Feng Chen ,  Ya-Shih Huang ,  Chun-Sheng Huang ,  Yiwei Chen

IPC: H03K5/15 ,  H03K5/135 ,  H03K5/00

Abstract: A clock buffer circuit is provided. The clock buffer circuit receives an input clock signal and generates a delay clock signal. The clock buffer circuit includes an input circuit, an output circuit, a first delay path, and a second delay path. The input circuit receives the input clock signal and generates an output clock signal according to the input clock signal. The output circuit generates the delay clock signal. The first delay path is coupled between the input circuit and the output circuit. The second delay path is coupled between the input circuit and the output circuit. The input circuit selectively provides the output clock signal to a first specific delay path among the first and second delay paths according to a control signal. The output circuit receives the output clock signal which passes through the first specific delay path and outputs the delay clock signal.

公开(公告)号：US09432001B2

公开(公告)日：2016-08-30

申请号：US14881505

申请日：2015-10-13

Applicant: MediaTek Inc.

Inventor： Yi-Feng Chen ,  Tsung-Ying Tsai ,  Heng-Meng Liu ,  Sung-Yun Hsueh

IPC: H03K3/03 ,  H03L7/00

CPC classification number: H03K3/0315 ,  H03K3/011 ,  H03L7/00

Abstract: A signal generator includes a main ring oscillator and a first ring oscillator. The main ring oscillator is supplied by a power voltage, and is configured to generate an output oscillation signal. The main ring oscillator is coupled through a power mesh to the power voltage. The first ring oscillator is supplied by the power voltage. The first ring oscillator is similar or identical to the main ring oscillator. The first ring oscillator is coupled through the power mesh to the power voltage. The first ring oscillator is used to calibrate a frequency of the output oscillation signal.

Abstract translation: 信号发生器包括主环形振荡器和第一环形振荡器。 主环形振荡器由电源电压提供，并被配置为产生输出振荡信号。 主环形振荡器通过功率网连接到电源电压。 第一个环形振荡器由电源电压供电。 第一个环形振荡器与主环形振荡器相似或相同。 第一个环形振荡器通过功率网耦合到电源电压。 第一个环形振荡器用于校准输出振荡信号的频率。