公开(公告)号：US11989005B2

公开(公告)日：2024-05-21

申请号：US17490663

申请日：2021-09-30

Applicant: MediaTek Inc.

Inventor： Bo-Jr Huang ,  Jia-Wei Fang ,  Jia-Ming Chen ,  Ya-Ting Chang ,  Chien-Yuan Lai ,  Cheng-Yuh Wu ,  Yi-Pin Lin ,  Wen-Wen Hsieh ,  Min-Shu Wang

IPC: G06F1/20 ,  G05B19/4155

CPC classification number: G05B19/4155 ,  G06F1/206 ,  G05B2219/50333

Abstract: A system performs adaptive thermal ceiling control at runtime. The system includes computing circuits and a thermal management module. When detecting a runtime condition change that affects power consumption in the system, the thermal management module determines an adjustment to the thermal ceiling of a computing circuit, and increases the thermal ceiling of the computing circuit according to the adjustment.

公开(公告)号：US20220334558A1

公开(公告)日：2022-10-20

申请号：US17490663

申请日：2021-09-30

Applicant: MediaTek Inc.

Inventor： Bo-Jr Huang ,  Jia-Wei Fang ,  Jia-Ming Chen ,  Ya-Ting Chang ,  Chien-Yuan Lai ,  Cheng-Yuh Wu ,  Yi-Pin Lin ,  Wen-Wen Hsieh ,  Min-Shu Wang

IPC: G05B19/4155

Abstract: A system performs adaptive thermal ceiling control at runtime. The system includes computing circuits and a thermal management module. When detecting a runtime condition change that affects power consumption in the system, the thermal management module determines an adjustment to the thermal ceiling of a computing circuit, and increases the thermal ceiling of the computing circuit according to the adjustment.

公开(公告)号：US09991879B2

公开(公告)日：2018-06-05

申请号：US15134954

申请日：2016-04-21

Applicant: MediaTek Inc.

Inventor： Bo-Jr Huang

IPC: H03K3/03 ,  H03K5/19 ,  G01R31/26

CPC classification number: H03K5/19 ,  G01R31/2621 ,  G01R31/2644 ,  G01R31/2884 ,  H03K3/0315

Abstract: A ring oscillator includes a plurality of inverters. A closed loop structure is formed by cascading the inverters. The inverter includes at least one sensitive inverter with a diode-connected transistor. A variation in an MOSFET (Metal Oxide Semiconductor Field Effect Transistor) threshold voltage of the ring oscillator is detected by analyzing the oscillation frequency of the ring oscillator.

公开(公告)号：US09897632B2

公开(公告)日：2018-02-20

申请号：US15014664

申请日：2016-02-03

Applicant: MediaTek Inc.

Inventor： Bo-Jr Huang

IPC: G01R11/32 ,  G01R31/08 ,  G01R19/00 ,  G01R21/00 ,  G06F1/28 ,  G01R19/252 ,  G01R1/20 ,  G01R19/25

CPC classification number: G01R19/0092 ,  G01R1/203 ,  G01R19/2503 ,  G01R19/252 ,  G01R21/00 ,  G06F1/28

Abstract: A monitor circuit for monitoring a CUT (Circuit Under Test) is provided. The monitor circuit includes a power switch and a current meter. The power switch is coupled between a supply voltage and the CUT. The current meter is coupled in parallel with the power switch. The current meter is configured to detect a current through the CUT.

公开(公告)号：US10067000B2

公开(公告)日：2018-09-04

申请号：US14855592

申请日：2015-09-16

Applicant: MediaTek Inc.

Inventor： Bo-Jr Huang ,  Yi-Feng Chen ,  Jia-Wei Fang

IPC: G01K7/01 ,  G01K7/00 ,  H03K3/03

Abstract: The invention provides an inverter. The inverter includes a first converter and a second converter. The first converter is coupled between a supply voltage and an output node of the inverter. The second converter is coupled between the output node of the inverter and a ground voltage. The first converter, the second converter, or both include diode-connected transistors. The propagation delay time of the inverter is substantially a linear function of the temperature of the inverter.

公开(公告)号：US09904752B2

公开(公告)日：2018-02-27

申请号：US14986275

申请日：2015-12-31

Applicant: MediaTek Inc.

Inventor： Zwei-Mei Lee ,  Bo-Jr Huang ,  Chi-Jih Shih ,  Jia-Wei Fang

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5009 ,  G06F17/505 ,  G06F2217/78

Abstract: A method for distributing power in the layout of an integrated circuit is provided. The integrated circuit includes at least one macro block. A first physical layout of the macro block is obtained, wherein the macro block includes a plurality of standard cells. The first physical layout is divided into a plurality of partitions according to an IR simulation result of the first physical layout. A plurality of power isolation cells are inserted between the partitions. A second physical layout is obtained according to the partitions and the power isolation cells. A macro placement of the macro block is obtained according to the second physical layout. Each of the partitions further includes a low drop out (LDO) regulator.

公开(公告)号：US09490808B2

公开(公告)日：2016-11-08

申请号：US14926775

申请日：2015-10-29

Applicant: MediaTek Inc.

Inventor： Bo-Jr Huang ,  Jia-Wei Fang

IPC: H03K17/296 ,  H03K19/003 ,  H03K5/14 ,  G06F1/24 ,  H03K17/22 ,  H03K19/20

CPC classification number: H03K19/00361 ,  G06F1/24 ,  H03K5/14 ,  H03K17/223 ,  H03K19/20

Abstract: A sensing circuit includes a delay chain and a decoder. The delay chain includes at least one delay unit, at least one cascading switch, and at least one feedback switch. The delay unit generates a delay signal according to an input signal and a reset signal. The cascading switch selectively passes the delay signal according to a control signal. The feedback switch selectively forms a feedback path of the delay unit according to the control signal. The decoder generates an output signal according to the delay signal. The delay unit is supplied by a work voltage. If the work voltage has noise, the noise will be detectable by analyzing the output signal of the decoder.

Abstract translation: 感测电路包括延迟链和解码器。 延迟链包括至少一个延迟单元，至少一个级联开关和至少一个反馈开关。 延迟单元根据输入信号和复位信号生成延迟信号。 级联开关根据控制信号选择性地传递延迟信号。 反馈开关根据控制信号选择性地形成延迟单元的反馈路径。 解码器根据延迟信号产生输出信号。 延迟单元由工作电压提供。 如果工作电压具有噪声，则可以通过分析解码器的输出信号来检测噪声。