Abstract:
Methods and apparatuses pertaining to hold-time compensation using free metal segments or other electrically-conductive segments of an IC are described. An integrated circuit (IC) having free segment hold-time compensation may include a monolithic semiconductor substrate which has a first device and a second device disposed thereon. In addition, the IC may include an electrical node electrically connecting the first and second devices. The electrical node may include one or more electrically-conductive elements that contribute to a total capacitance at the electrical node such that the total capacitance at the electrical node has a value that fulfills a hold-time requirement at the electrical node.
Abstract:
A feedthrough signal transmission apparatus, fabricated on a single silicon, includes a plurality of feedthrough signal transmission circuits and a permanently on control cell that is coupled to the feedthrough signal transmission circuits, where each feedthrough signal transmission circuit of the feedthrough signal transmission circuits may include at least one sub-circuit that is kept in a power on state when the sub-circuit performs feedthrough signal transmission. For example, and the sub-circuit may include a permanently on-for-feedthrough repeater (e.g. a repeater that is kept in the power on state when the repeater performs feedthrough signal transmission). In addition, the permanently on control cell may be configured to maintain the power on state of the sub-circuit when the sub-circuit performs feedthrough signal transmission. For example, sub-circuits of the feedthrough signal transmission circuits are located at grid-based locations, respectively.
Abstract:
An integrated circuit (IC) may include a plurality of functional blocks, and each functional block of the plurality of functional blocks may include hardware circuits, wherein the plurality of functional blocks may include a first functional block. In addition, the first functional block may include a first macro circuit that is positioned within a first sub-region of the first functional block, wherein among multiple sides of the first sub-region, a first side of the first sub-region is closest to a boundary of the first functional block. Additionally, a first intermediate sub-region of the first functional block is positioned between the first side of the first sub-region and the boundary of the first functional block, and there is no tap cell in the first intermediate sub-region of the first functional block.
Abstract:
A semiconductor structure includes a first spare cell region, a first conductive line and a second conductive line. The first spare cell region has a plurality of spare cells. The first conductive line is coupled between a first reference voltage and the plurality of spare cells, and is arranged for providing the first reference voltage to the plurality of spare cells of the first spare cell region. The second conductive line is coupled to a plurality of spare cells, and is arranged for providing a second reference voltage to the plurality of spare cells of the first spare cell region.
Abstract:
A feedthrough signal transmission circuit includes a first permanently on cell and a cell controlling unit. The first permanently on cell is arranged to transmit a first control signal. The cell controlling unit is coupled to the first permanently on cell, and includes a power switch and a plurality o buffers. The power switch is coupled to the first permanently on cell, arranged to receive a switch control signal and the first control signal, and selectively output the first control signal according to the switch control signal. The plurality of buffers is coupled to the power switch. Each of the buffers is arranged to buffer a data input only when powered by the first control signal output from the power switch.
Abstract:
A feedthrough signal transmission circuit includes a first permanently on cell and a cell controlling unit. The first permanently on cell is arranged to transmit a first control signal. The cell controlling unit is coupled to the first permanently on cell, and includes a power switch and a plurality o buffers. The power switch is coupled to the first permanently on cell, arranged to receive a switch control signal and the first control signal, and selectively output the first control signal according to the switch control signal. The plurality of buffers is coupled to the power switch. Each of the buffers is arranged to buffer a data input only when powered by the first control signal output from the power switch.
Abstract:
A method for arranging an integrated circuit to correct a hold-time violation is provided. A first layout of the integrated circuit is prepared. The first layout includes a plurality of cells including a plurality of cell pins, wires connected between the cells, and one of the cell pins is located in a preservation area. The hold-time violation of the first layout is estimated to obtain an estimation result. A dummy wire structure is designed to be placed in the preservation area according to the estimation result to correct the hold-time violation. The dummy wire structure only contacts the cell pin in the preservation area. A second layout is generated according to the first layout and the designed dummy wire structure. The integrated circuit is arranged according to the second layout.