公开(公告)号：US10126951B2

公开(公告)日：2018-11-13

申请号：US14905970

申请日：2015-06-16

Applicant: MEDIATEK INC.

Inventor： Kun-Bin Lee ,  Tung-Hsing Wu ,  Yi-Hao Wu

IPC: G06F3/06 ,  G06F5/00 ,  G06F13/16

Abstract: A data processing apparatus includes a storage element and a clock controller. The storage element has storage partitions, including a first storage partition and a second storage partition. The clock controller controls clock driving of the first storage partition and the second storage partition. When a processing circuit is configured to operate in a first condition to process a first data sample with a first bit width, the clock controller enables clock driving of both of the first storage partition and the second storage partition. When the processing circuit is configured to operate in a second condition to process a second data sample with a second bit width, the clock controller enables clock driving of the first storage partition and disables clock driving of the second storage partition.

公开(公告)号：US20160154583A1

公开(公告)日：2016-06-02

申请号：US14905970

申请日：2015-06-16

Applicant: MEDIATEK INC.

Inventor： Kun-Bin Lee ,  Tung-Hsing Wu ,  Yi-Hao Wu

IPC: G06F3/06 ,  G06F13/16

CPC classification number: G06F3/061 ,  G06F3/0631 ,  G06F3/0644 ,  G06F3/0673 ,  G06F5/00 ,  G06F13/1689 ,  Y02D10/14

Abstract: A data processing apparatus includes a storage element and a clock controller. The storage element has storage partitions, including a first storage partition and a second storage partition. The clock controller controls clock driving of the first storage partition and the second storage partition. When a processing circuit is configured to operate in a first condition to process a first data sample with a first bit width, the clock controller enables clock driving of both of the first storage partition and the second storage partition. When the processing circuit is configured to operate in a second condition to process a second data sample with a second bit width, the clock controller enables clock driving of the first storage partition and disables clock driving of the second storage partition.

Abstract translation: 数据处理装置包括存储元件和时钟控制器。 存储元件具有存储分区，包括第一存储分区和第二存储分区。 时钟控制器控制第一存储分区和第二存储分区的时钟驱动。 当处理电路被配置为在第一条件下操作以处理具有第一位宽度的第一数据样本时，时钟控制器启用第一存储分区和第二存储分区两者的时钟驱动。 当处理电路被配置为在第二状态下操作以处理具有第二位宽度的第二数据样本时，时钟控制器使得能够进行第一存储分区的时钟驱动并禁止第二存储分区的时钟驱动。