公开(公告)号：US12106822B2

公开(公告)日：2024-10-01

申请号：US17852193

申请日：2022-06-28

Applicant: MEDIATEK Singapore Pte. Ltd.

Inventor： Chetan Deshpande ,  Gajanan Sahebrao Jedhe ,  Gaurang Prabhakar Narvekar ,  Cheng-Xin Xue ,  Sushil Kumar ,  Zijie Guo

IPC: G11C7/10 ,  G06F7/501 ,  G06F7/544 ,  G11C7/12 ,  G11C8/06 ,  G11C8/08

CPC classification number: G11C7/1069 ,  G06F7/501 ,  G06F7/5443 ,  G11C7/1012 ,  G11C7/1096 ,  G11C7/12 ,  G11C8/06 ,  G11C8/08

Abstract: Aspects of the present disclosure are directed to devices and methods for performing MAC operations using a memory array as a compute-in-memory (CIM) device that can enable higher computational throughput, higher performance and lower energy consumption compared to computation using a processor outside of a memory array. In some embodiments, an activation architecture is provided using a bit cell array arranged in rows and columns to store charges that represent a weight value in a weight matrix. A read word line (RWL) may be repurposed to provide the input activation value to bit cells within a row of bit cells, while a read-bit line (RBL) is configured to receive multiplication products from bit cells arranged in a column. Some embodiments provide multiple sub-arrays or tiles of bit cell arrays.

公开(公告)号：US20230022347A1

公开(公告)日：2023-01-26

申请号：US17852193

申请日：2022-06-28

Applicant: MEDIATEK Singapore Pte. Ltd.

Inventor： Chetan Deshpande ,  Gajanan Sahebaro Jedhe ,  Gaurang Prabhakar Narvekar ,  Cheng-Xin Xue ,  Sushil Kumar ,  Zijie Guo

IPC: G11C7/10 ,  G11C7/12 ,  G11C8/08 ,  G11C8/06 ,  G06F7/544 ,  G06F7/501

Abstract: Aspects of the present disclosure are directed to devices and methods for performing MAC operations using a memory array as a compute-in-memory (CIM) device that can enable higher computational throughput, higher performance and lower energy consumption compared to computation using a processor outside of a memory array. In some embodiments, an activation architecture is provided using a bit cell array arranged in rows and columns to store charges that represent a weight value in a weight matrix. A read word line (RWL) may be repurposed to provide the input activation value to bit cells within a row of bit cells, while a read-bit line (RBL) is configured to receive multiplication products from bit cells arranged in a column. Some embodiments provide multiple sub-arrays or tiles of bit cell arrays.

公开(公告)号：US20220328099A1

公开(公告)日：2022-10-13

申请号：US17709183

申请日：2022-03-30

Applicant: MEDIATEK Singapore Pte. Ltd.

Inventor： Chetan Deshpande ,  Gajanan Sahebrao Jedhe ,  Cheng-Xin Xue ,  Zijie Guo

IPC: G11C15/04 ,  G06F7/523 ,  G06F7/50 ,  G11C11/412

Abstract: Aspects of the present disclosure are directed to devices and methods for performing MAC operations using a TCAM array as a compute-in-memory (CIM) device that can enable higher computational throughput, higher performance and lower energy consumption compared to computation using a processor outside of a memory array. In some embodiments, weights in a weight matrix may be programmed in SRAMs of a TCAM bit cell array. Each SRAM may operate as a multiplier that performs a multiplication between the stored weight to an input activation value applied at a search line in the TCAM bit cell array. The two SRAMs within a TCAM bit cell may operate independently to receive independently two input activation values on their respective select lines, and to perform a multiplication operation with the stored weight in each respective SRAM.