公开(公告)号：US20230022347A1

公开(公告)日：2023-01-26

申请号：US17852193

申请日：2022-06-28

Applicant: MEDIATEK Singapore Pte. Ltd.

Inventor： Chetan Deshpande ,  Gajanan Sahebaro Jedhe ,  Gaurang Prabhakar Narvekar ,  Cheng-Xin Xue ,  Sushil Kumar ,  Zijie Guo

IPC: G11C7/10 ,  G11C7/12 ,  G11C8/08 ,  G11C8/06 ,  G06F7/544 ,  G06F7/501

Abstract: Aspects of the present disclosure are directed to devices and methods for performing MAC operations using a memory array as a compute-in-memory (CIM) device that can enable higher computational throughput, higher performance and lower energy consumption compared to computation using a processor outside of a memory array. In some embodiments, an activation architecture is provided using a bit cell array arranged in rows and columns to store charges that represent a weight value in a weight matrix. A read word line (RWL) may be repurposed to provide the input activation value to bit cells within a row of bit cells, while a read-bit line (RBL) is configured to receive multiplication products from bit cells arranged in a column. Some embodiments provide multiple sub-arrays or tiles of bit cell arrays.

公开(公告)号：US11967377B2

公开(公告)日：2024-04-23

申请号：US17522214

申请日：2021-11-09

Applicant: MediaTek Singapore Pte. Ltd.

Inventor： Chetan Deshpande ,  Sushil Kumar ,  Gajanan Sahebrao Jedhe ,  Ritesh Garg ,  Gaurang Prabhakar Narvekar

IPC: G11C15/04

CPC classification number: G11C15/04

Abstract: A content addressable memory (CAM) device includes multiple CAM sub-banks Each CAM sub-bank includes an array of CAM cells arranged in rows and columns and partitioned into a first stage and a second stage along a column dimension. Each CAM sub-bank further includes first-stage match lines (MLs), first-stage search line (SL) pairs, second-stage MLs, and second-stage SL pairs. Each second-stage SL pair is coupled to a column of CAM cells in the second stage and is gated by an SL enable (SL_EN signal). Each CAM sub-bank further includes a circuit operative to receive all of the first-stage MLs as input and de-assert the SL_EN signal when none of the first-stage MLs indicate a match. De-assertion of the SL_EN signal blocks a second portion search key from being provided to the second-stage SL pairs.

公开(公告)号：US12106822B2

公开(公告)日：2024-10-01

申请号：US17852193

申请日：2022-06-28

Applicant: MEDIATEK Singapore Pte. Ltd.

Inventor： Chetan Deshpande ,  Gajanan Sahebrao Jedhe ,  Gaurang Prabhakar Narvekar ,  Cheng-Xin Xue ,  Sushil Kumar ,  Zijie Guo

IPC: G11C7/10 ,  G06F7/501 ,  G06F7/544 ,  G11C7/12 ,  G11C8/06 ,  G11C8/08

CPC classification number: G11C7/1069 ,  G06F7/501 ,  G06F7/5443 ,  G11C7/1012 ,  G11C7/1096 ,  G11C7/12 ,  G11C8/06 ,  G11C8/08

Abstract: Aspects of the present disclosure are directed to devices and methods for performing MAC operations using a memory array as a compute-in-memory (CIM) device that can enable higher computational throughput, higher performance and lower energy consumption compared to computation using a processor outside of a memory array. In some embodiments, an activation architecture is provided using a bit cell array arranged in rows and columns to store charges that represent a weight value in a weight matrix. A read word line (RWL) may be repurposed to provide the input activation value to bit cells within a row of bit cells, while a read-bit line (RBL) is configured to receive multiplication products from bit cells arranged in a column. Some embodiments provide multiple sub-arrays or tiles of bit cell arrays.

公开(公告)号：US20220223207A1

公开(公告)日：2022-07-14

申请号：US17522214

申请日：2021-11-09

Applicant: MediaTek Singapore Pte. Ltd.

Inventor： Chetan Deshpande ,  Sushil Kumar ,  Gajanan Sahebrao Jedhe ,  Ritesh Garg ,  Gaurang Prabhakar Narvekar

IPC: G11C15/04

Abstract: A content addressable memory (CAM) device includes multiple CAM sub-banks Each CAM sub-bank includes an array of CAM cells arranged in rows and columns and partitioned into a first stage and a second stage along a column dimension. Each CAM sub-bank further includes first-stage match lines (MLs), first-stage search line (SL) pairs, second-stage MLs, and second-stage SL pairs. Each second-stage SL pair is coupled to a column of CAM cells in the second stage and is gated by an SL enable (SL_EN signal). Each CAM sub-bank further includes a circuit operative to receive all of the first-stage MLs as input and de-assert the SL_EN signal when none of the first-stage MLs indicate a match. De-assertion of the SL_EN signal blocks a second portion search key from being provided to the second-stage SL pairs.