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公开(公告)号：US10778406B2
公开(公告)日：2020-09-15
申请号：US16199312
申请日：2018-11-26
Applicant: Mellanox Technologies, Ltd.
Inventor： Chen Gaist , Ran Ravid , Aviv Berg , Lavi Koch
IPC: H04L7/04
Abstract: A network device including frequency generation circuitry configured to generate a clock signal, a phase-locked loop configured to generate a local clock based on the clock signal, a plurality of receivers configured to receive respective data streams from respective remote clock sources, each receiver of the plurality of receivers being configured to recover a remote clock from a respective data stream, and a controller configured to identify the remote clock recovered by one of the plurality of receivers as a master clock, find a clock differential between the identified remote clock and the local clock, provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuit to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential.
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公开(公告)号：US11637557B2
公开(公告)日：2023-04-25
申请号：US17670540
申请日：2022-02-14
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Ran Ravid , Aviv Berg , Lavi Koch , Chen Gaist , Dotan David Levi
Abstract: In one embodiment, a device includes frequency generation circuitry configured to generate a clock signal, a phase-locked loop (PLL) configured to generate a local clock based on the clock signal, a receiver configured to receive a data stream from a remote clock source and recover a remote clock from the data stream, and a controller configured to find a clock differential between the local clock and the remote clock identified as a master dock, and provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuitry to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential between the local clock and the remote clock identified as the master clock so that the local clock generated by the PLL is synchronized with the master clock.
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公开(公告)号：US20220021393A1
公开(公告)日：2022-01-20
申请号：US16920772
申请日：2020-07-06
Applicant: Mellanox Technologies, Ltd.
Inventor： Ran Ravid , Aviv Berg , Lavi Koch , Chen Gaist , Dotan David Levi
Abstract: In one embodiment, a network device includes frequency generation circuitry configured to generate a clock signal, a phase-locked loop (PLL) configured to generate a local clock based on the clock signal, a plurality of receivers configured to receive respective data streams from respective remote clock sources, each receiver of the plurality of receivers being configured to recover a remote clock from a respective data stream, and a controller configured to identify the remote clock recovered by one of the plurality of receivers as a master clock, find a clock differential between the identified remote clock and the local clock, and provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuitry to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential.
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Patent Agency Ranking
公开(公告)号：US10686630B1
公开(公告)日：2020-06-16
申请号：US16511771
申请日：2019-07-15
Applicant: Mellanox Technologies, Ltd.
Inventor： Eyal David , Shai Cohen , Johan Jacob Mohr , Daniel Kedar , Stanislav Gurtovoy , Ran Sela , Aviv Berg
Abstract: Embodiments are disclosed for channel estimation in a receiver of a communication system. An example method includes receiving, via a receiver of a communication system, an input signal. The example method further includes using a first event indicator embedded in an analog circuit of the receiver to slice the input signal to generate a sliced input signal and applying an offset to the input signal to generate an offsetted signal. The example method further includes using a second event indicator embedded in the analog circuit to slice the offsetted signal to generate a sliced offsetted signal. The example method further includes applying a first predefined delay to the sliced input signal and applying a second predefined delay to the sliced offsetted signal. The example method further includes generating a conditional ones signal based on the sliced input signal and the sliced offsetted signal and using the conditional ones signal to calibrate an equalizer embedded in the receiver.
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公开(公告)号：US20240064443A1
公开(公告)日：2024-02-22
申请号：US17948930
申请日：2022-09-20
Applicant: Mellanox Technologies, Ltd.
Inventor： Ioannis (Giannis) Patronas , Paraskevas Bakopoulos , Dotan David Levi , Aviv Berg , Wojciech Wasko , Dimitrios Syrivelis , Elad Mentovich , Yoav Rozenberg , Nikolaos Argyris
IPC: H04Q11/00
CPC classification number: H04Q11/0005 , H04Q11/0062 , H04Q2011/0007 , H04Q2011/0037 , H04Q2011/0064
Abstract: Systems, devices, and methods are described herein for reducing a link bringup time period for optical switching between network devices. An example method of the present disclosure receives an indication of a reconfiguration condition associated with an optical switch communicatively coupled to an optical communication channel and based on the reconfiguration condition, selects first data associated with a storage device or second data associated with a pattern generator device for transmission to a first network device. Selecting the first or second data may be based on a digital logic signal that indicates whether data is actively received from the second network device via the optical communication channel or may be based on a defined schedule for reconfiguring the optical switch.
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公开(公告)号：US11283454B2
公开(公告)日：2022-03-22
申请号：US16920772
申请日：2020-07-06
Applicant: Mellanox Technologies, Ltd.
Inventor： Ran Ravid , Aviv Berg , Lavi Koch , Chen Gaist , Dotan David Levi
Abstract: In one embodiment, a network device includes frequency generation circuitry configured to generate a clock signal, a phase-locked loop (PLL) configured to generate a local clock based on the clock signal, a plurality of receivers configured to receive respective data streams from respective remote clock sources, each receiver of the plurality of receivers being configured to recover a remote clock from a respective data stream, and a controller configured to identify the remote clock recovered by one of the plurality of receivers as a master clock, find a clock differential between the identified remote clock and the local clock, and provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuitry to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential.
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公开(公告)号：US20220173741A1
公开(公告)日：2022-06-02
申请号：US17670540
申请日：2022-02-14
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Ran Ravid , Aviv Berg , Lavi Koch , Chen Gaist , Dotan David Levi
Abstract: In one embodiment, a device includes frequency generation circuitry configured to generate a clock signal, a phase-locked loop (PLL) configured to generate a local clock based on the clock signal, a receiver configured to receive a data stream from a remote clock source and recover a remote clock from the data stream, and a controller configured to find a clock differential between the local clock and the remote clock identified as a master dock, and provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuitry to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential between the local clock and the remote clock identified as the master clock so that the local clock generated by the PLL is synchronized with the master clock.
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公开(公告)号：US20200169379A1
公开(公告)日：2020-05-28
申请号：US16199312
申请日：2018-11-26
Applicant: Mellanox Technologies, Ltd.
Inventor： Chen Gaist , Ran Ravid , Aviv Berg , Lavi Koch
IPC: H04L7/04
Abstract: A network device including frequency generation circuitry configured to generate a clock signal, a phase-locked loop configured to generate a local clock based on the clock signal, a plurality of receivers configured to receive respective data streams from respective remote clock sources, each receiver of the plurality of receivers being configured to recover a remote clock from a respective data stream, and a controller configured to identify the remote clock recovered by one of the plurality of receivers as a master clock, find a clock differential between the identified remote clock and the local clock, provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuit to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential.
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