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公开(公告)号：US20240039689A1
公开(公告)日：2024-02-01
申请号：US17994326
申请日：2022-11-27
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Roman Meltser , Guy Lederman , Ran Ravid , Zvi Rechtman , Lavi Koch
IPC: H04L7/02
CPC classification number: H04L7/02
Abstract: In one embodiment, a retimer device includes a receiver to receive data from a first device via a data link, retimer circuitry to recover a clock phase from the received data, and prepare a new copy of the received data sampled by a clean clock based on the recovered clock phase, a transmitter to transmit the new copy to a second device via the data link, wherein the receiver is configured to receive an in-band standby signal from the first device having a given pattern in a physical layer of the signal, activate a power saving mode of the retimer device responsively to the standby signal having the given pattern in the physical layer of the standby signal, receive an in-band wakeup signal from the first device, and initiate an exit from the power saving mode to power up the retimer device responsively to the wakeup signal.
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公开(公告)号：US11283454B2
公开(公告)日：2022-03-22
申请号：US16920772
申请日：2020-07-06
Applicant: Mellanox Technologies, Ltd.
Inventor： Ran Ravid , Aviv Berg , Lavi Koch , Chen Gaist , Dotan David Levi
Abstract: In one embodiment, a network device includes frequency generation circuitry configured to generate a clock signal, a phase-locked loop (PLL) configured to generate a local clock based on the clock signal, a plurality of receivers configured to receive respective data streams from respective remote clock sources, each receiver of the plurality of receivers being configured to recover a remote clock from a respective data stream, and a controller configured to identify the remote clock recovered by one of the plurality of receivers as a master clock, find a clock differential between the identified remote clock and the local clock, and provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuitry to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential.
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公开(公告)号：US20220070117A1
公开(公告)日：2022-03-03
申请号：US17010892
申请日：2020-09-03
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Sagi Rotem , Zvi Rechtman , Lavi Koch , Roee Shapiro
IPC: H04L12/935 , G06F9/4401
Abstract: A network element includes at least one communication port and a processor. The communication port is configured to communicate with a peer communication port of a peer network element. The processor is configured to support a full-boot mode and a fast-boot mode, to establish, by negotiation with the peer network element, whether the fast-boot mode is supported both for the communication port and for the peer communication port, and, in response to finding that the fast-boot mode is supported both for the communication port and for the peer communication port, to coordinate with the peer network element a boot of the communication port and of the peer communication port, both using the fast-boot mode.
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公开(公告)号：US10778406B2
公开(公告)日：2020-09-15
申请号：US16199312
申请日：2018-11-26
Applicant: Mellanox Technologies, Ltd.
Inventor： Chen Gaist , Ran Ravid , Aviv Berg , Lavi Koch
IPC: H04L7/04
Abstract: A network device including frequency generation circuitry configured to generate a clock signal, a phase-locked loop configured to generate a local clock based on the clock signal, a plurality of receivers configured to receive respective data streams from respective remote clock sources, each receiver of the plurality of receivers being configured to recover a remote clock from a respective data stream, and a controller configured to identify the remote clock recovered by one of the plurality of receivers as a master clock, find a clock differential between the identified remote clock and the local clock, provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuit to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential.
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5.发明申请公开(公告)号：US20160062442A1
公开(公告)日：2016-03-03
申请号：US14836988
申请日：2015-08-27
Applicant: MELLANOX TECHNOLOGIES LTD.
Inventor： Idan Burstein , Shlomo Raikin , Noam Bloch , Lavi Koch
IPC: G06F1/32
CPC classification number: G06F1/3209 , G06F1/266 , G06F1/324 , H04L12/10 , Y02D10/126 , Y02D50/20
Abstract: A method for processing data includes receiving in a peripheral device, which is connected by a bus to a host processor having host resources, a notification of a sleep state of at least one of the host resources. While the at least one of the host resources is in the sleep state, when the peripheral device receives data from a data source for delivery to the host processor, the peripheral device sends a message to the data source, which causes the data source to defer conveying further data to the peripheral device until the at least one of the host resources has awakened from the sleep state.
Abstract translation: 一种用于处理数据的方法包括：在通过总线连接到具有主机资源的主处理器的外围设备中接收至少一个主机资源的睡眠状态的通知。 当主机资源中的至少一个处于睡眠状态时，当外围设备从数据源接收数据以传送到主处理器时，外围设备向数据源发送消息，这导致数据源延迟 将进一步的数据传送到外围设备，直到主机资源中的至少一个已经从睡眠状态唤醒。
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Patent Agency Ranking
公开(公告)号：US11349780B2
公开(公告)日：2022-05-31
申请号：US17010892
申请日：2020-09-03
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Sagi Rotem , Zvi Rechtman , Lavi Koch , Roee Shapiro
IPC: H04L1/00 , H04L49/00 , G06F9/4401
Abstract: A network element includes at least one communication port and a processor. The communication port is configured to communicate with a peer communication port of a peer network element. The processor is configured to support a full-boot mode and a fast-boot mode, to establish, by negotiation with the peer network element, whether the fast-boot mode is supported both for the communication port and for the peer communication port, and, in response to finding that the fast-boot mode is supported both for the communication port and for the peer communication port, to coordinate with the peer network element a boot of the communication port and of the peer communication port, both using the fast-boot mode.
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公开(公告)号：US20220021393A1
公开(公告)日：2022-01-20
申请号：US16920772
申请日：2020-07-06
Applicant: Mellanox Technologies, Ltd.
Inventor： Ran Ravid , Aviv Berg , Lavi Koch , Chen Gaist , Dotan David Levi
Abstract: In one embodiment, a network device includes frequency generation circuitry configured to generate a clock signal, a phase-locked loop (PLL) configured to generate a local clock based on the clock signal, a plurality of receivers configured to receive respective data streams from respective remote clock sources, each receiver of the plurality of receivers being configured to recover a remote clock from a respective data stream, and a controller configured to identify the remote clock recovered by one of the plurality of receivers as a master clock, find a clock differential between the identified remote clock and the local clock, and provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuitry to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential.
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公开(公告)号：US11637557B2
公开(公告)日：2023-04-25
申请号：US17670540
申请日：2022-02-14
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Ran Ravid , Aviv Berg , Lavi Koch , Chen Gaist , Dotan David Levi
Abstract: In one embodiment, a device includes frequency generation circuitry configured to generate a clock signal, a phase-locked loop (PLL) configured to generate a local clock based on the clock signal, a receiver configured to receive a data stream from a remote clock source and recover a remote clock from the data stream, and a controller configured to find a clock differential between the local clock and the remote clock identified as a master dock, and provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuitry to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential between the local clock and the remote clock identified as the master clock so that the local clock generated by the PLL is synchronized with the master clock.
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公开(公告)号：US20240056380A1
公开(公告)日：2024-02-15
申请号：US18174701
申请日：2023-02-27
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Zvi Rechtman , Guy Lederman , Stanislav Gurtovoy , Ran Ravid , Lavi Koch , Oded Nadir
Abstract: In one embodiment, a multi-segment communication network system includes nodes connected via links, a first node including a first receiver and transmitter, and a second node including a second receiver and transmitter, wherein the first transmitter is to transmit a link training frame including a training pattern to the second receiver, which is to receive the link training frame, the second node is to find a tuning factor to which to tune the first transmitter responsively to the training pattern, and generate a request indicative of the found tuning factor, the second transmitter is to send the request in the link training frame via a plurality of the links to the first receiver, the first receiver is to receive the request, and the first node is to tune at least one parameter of the first transmitter based on the tuning factor indicated in the request.
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公开(公告)号：US20220173741A1
公开(公告)日：2022-06-02
申请号：US17670540
申请日：2022-02-14
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Ran Ravid , Aviv Berg , Lavi Koch , Chen Gaist , Dotan David Levi
Abstract: In one embodiment, a device includes frequency generation circuitry configured to generate a clock signal, a phase-locked loop (PLL) configured to generate a local clock based on the clock signal, a receiver configured to receive a data stream from a remote clock source and recover a remote clock from the data stream, and a controller configured to find a clock differential between the local clock and the remote clock identified as a master dock, and provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuitry to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential between the local clock and the remote clock identified as the master clock so that the local clock generated by the PLL is synchronized with the master clock.
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