公开(公告)号：US11741232B2

公开(公告)日：2023-08-29

申请号：US17163599

申请日：2021-02-01

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Mor Hoyda Sfadia ,  Yuval Itkin ,  Ahmad Atamli ,  Ariel Shahar ,  Yaniv Strassberg ,  Itsik Levi

IPC: G06F21/57 ,  G06F8/65 ,  G06F9/445

CPC classification number: G06F21/572 ,  G06F8/65 ,  G06F9/445 ,  G06F2221/033

Abstract: A computer system includes a volatile memory and at least one processor. The volatile memory includes a protected storage segment (PSS) configured to store firmware-authentication program code for authenticating firmware of the computer system. The at least one processor is configured to receive a trigger to switch to a given version of the firmware, to obtain, in response to the trigger, a privilege to access the PSS, to authenticate the given version of the firmware by executing the firmware-authentication program code from the PSS, to switch to the given version of the firmware upon successfully authenticating the given version, and to take an alternative action upon failing to authenticate the given version.

公开(公告)号：US11734005B2

公开(公告)日：2023-08-22

申请号：US17367367

申请日：2021-07-04

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Zachy Haramaty ,  Yaniv Strassberg ,  Itsik Levi ,  Alon Singer

IPC: G06F9/30 ,  G06F12/02

CPC classification number: G06F9/30101 ,  G06F12/023 ,  G06F2212/251

Abstract: An apparatus includes a processor and split-read control circuitry (SRCC). The processor is to issue a set of one or more split-read requests for loading one or more data values to one or more respective local registers of the processor. The SRCC is to receive the set of one or more split-read requests, to read the one or more data values on behalf of the processor, and to write the data values into the one or more respective local registers. The processor and the SRCC are to coordinate a status of the split-read requests via a split-read-status indication.

公开(公告)号：US20220245251A1

公开(公告)日：2022-08-04

申请号：US17163599

申请日：2021-02-01

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Mor Hoyda Sfadia ,  Yuval Itkin ,  Ahmad Atamli ,  Ariel Shahar ,  Yaniv Strassberg ,  Itsik Levi

IPC: G06F21/57 ,  G06F8/65 ,  G06F9/445

Abstract: A computer system includes a volatile memory and at least one processor. The volatile memory includes a protected storage segment (PSS) configured to store firmware-authentication program code for authenticating firmware of the computer system. The at least one processor is configured to receive a trigger to switch to a given version of the firmware, to obtain, in response to the trigger, a privilege to access the PSS, to authenticate the given version of the firmware by executing the firmware-authentication program code from the PSS, to switch to the given version of the firmware upon successfully authenticating the given version, and to take an alternative action upon failing to authenticate the given version.

公开(公告)号：US20230004392A1

公开(公告)日：2023-01-05

申请号：US17367367

申请日：2021-07-04

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Zachy Haramaty ,  Yaniv Strassberg ,  Itsik Levi ,  Alon Singer

IPC: G06F9/30 ,  G06F12/02

Abstract: An apparatus includes a processor and split-read control circuitry (SRCC). The processor is to issue a set of one or more split-read requests for loading one or more data values to one or more respective local registers of the processor. The SRCC is to receive the set of one or more split-read requests, to read the one or more data values on behalf of the processor, and to write the data values into the one or more respective local registers. The processor and the SRCC are to coordinate a status of the split-read requests via a split-read-status indication.

公开(公告)号：US20190095776A1

公开(公告)日：2019-03-28

申请号：US15716761

申请日：2017-09-27

Applicant: Mellanox Technologies, Ltd.

Inventor： Boaz Kfir ,  Noam Eilon ,  Meital Tsechanski ,  Itsik Levi

IPC: G06N3/04 ,  G06F9/30

Abstract: Computational apparatus includes an input buffer configured to hold a first array of input data and an output buffer configured to hold a second array of output data computed by the apparatus. A plurality of processing elements are each configured to compute a convolution of a respective kernel with a set of the input data that are contained within a respective window and to write a result of the convolution to a corresponding location in a respective plane of the output data. One or more data fetch units each read one or more segments of the input data from the input buffer. A shift register delivers the segments of the input data in succession to each of the processing elements in an order selected so that the respective window of each processing element slides in turn over a sequence of window positions covering the first array.

公开(公告)号：US12223051B2

公开(公告)日：2025-02-11

申请号：US18349147

申请日：2023-07-09

Applicant: Mellanox Technologies, Ltd.

Inventor： Mor Hoyda Sfadia ,  Yuval Itkin ,  Ahmad Atamli ,  Ariel Shahar ,  Yaniv Strassberg ,  Itsik Levi

IPC: G06F21/57 ,  G06F8/65 ,  G06F9/445

Abstract: A computer system includes a volatile memory and at least one processor. The volatile memory includes a protected storage segment (PSS) configured to store firmware-authentication program code for authenticating firmware of the computer system. The at least one processor is configured to receive a trigger to switch to a given version of the firmware, to obtain, in response to the trigger, a privilege to access the PSS, to authenticate the given version of the firmware by executing the firmware-authentication program code from the PSS, to switch to the given version of the firmware upon successfully authenticating the given version, and to take an alternative action upon failing to authenticate the given version.

公开(公告)号：US20230351021A1

公开(公告)日：2023-11-02

申请号：US18349147

申请日：2023-07-09

Applicant: Mellanox Technologies, Ltd.

Inventor： Mor Hoyda Sfadia ,  Yuval Itkin ,  Ahmad Atamli ,  Ariel Shahar ,  Yaniv Strassberg ,  Itsik Levi

IPC: G06F21/57 ,  G06F8/65 ,  G06F9/445

CPC classification number: G06F21/572 ,  G06F8/65 ,  G06F9/445 ,  G06F2221/033

Abstract: A computer system includes a volatile memory and at least one processor. The volatile memory includes a protected storage segment (PSS) configured to store firmware-authentication program code for authenticating firmware of the computer system. The at least one processor is configured to receive a trigger to switch to a given version of the firmware, to obtain, in response to the trigger, a privilege to access the PSS, to authenticate the given version of the firmware by executing the firmware-authentication program code from the PSS, to switch to the given version of the firmware upon successfully authenticating the given version, and to take an alternative action upon failing to authenticate the given version.