Offloaded intra-system synchronization

    公开(公告)号:US20250093905A1

    公开(公告)日:2025-03-20

    申请号:US18470452

    申请日:2023-09-20

    Abstract: In one embodiment, a peripheral device includes an oscillator, a counter to be driven by the oscillator and provide a peripheral device counter value, and processing circuitry to receive a host device counter value from a host device, read host device clock translation parameters from a host memory of the host device, the host device clock translation parameters providing translation between the host device counter value and a host device clock time, read peripheral device clock translation parameters providing a translation between the peripheral device counter value and a peripheral device clock time, read the peripheral device counter value, compute a clock correction as a function of a difference between the host device clock time and the peripheral clock time, based on the host device and peripheral device counter values and clock translation parameters, and correct the host device or peripheral device clock translation parameters based on the clock correction.

    Clock synchronization monitoring system

    公开(公告)号:US20250021130A1

    公开(公告)日:2025-01-16

    申请号:US18349976

    申请日:2023-07-11

    Abstract: In one embodiment, a system including a reference processing device includes a reference hardware clock to maintain a reference clock value, and reference clock synchronization circuitry to discipline the reference hardware clock responsively to a remote clock, which is remote to the system, and a follower processing device including a follower hardware clock to maintain a follower clock value, and follower clock synchronization circuitry to synchronize the follower hardware clock to the reference hardware clock, and provide an indication about the follower clock value to the reference processing device, wherein the reference clock synchronization circuitry is configured to monitor a quality of the synchronization of the follower hardware clock to the reference hardware clock.

    Clock synchronization using digitally controlled oscillator

    公开(公告)号:US20250055667A1

    公开(公告)日:2025-02-13

    申请号:US18420822

    申请日:2024-01-24

    Abstract: In one embodiment, a system, includes a digitally controlled oscillator (DCO) to generate a local clock signal having a local clock frequency, and a hardware clock to maintain a value indicative of a local clock time advancing at a frequency proportional to the local clock frequency of the local clock signal generated by the DCO, and clock synchronization circuitry to receive from a device an indication of a remote clock time, generate a digital control command to at least partially correct for a difference between the remote clock time and the local clock time, and provide the digital control command to the DCO, wherein the DCO is to adjust the local clock frequency responsively to the digital control command.

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