公开(公告)号：US20210400124A1

公开(公告)日：2021-12-23

申请号：US16908776

申请日：2020-06-23

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Ilan Pardo ,  Mark B. Rosenbluth ,  Idan Burstein ,  Rui Xu ,  Oded Lempel ,  Tsofia Eshel

IPC: H04L29/06 ,  G06F12/0875 ,  G06F13/40 ,  H04L29/08 ,  H04L12/879

Abstract: In one embodiment, a computer system includes a payload sub-system including interfaces to connect with respective devices, transfer data with the respective devices, and receive write transactions from the respective devices, a classifier to classify the received write transactions into payload data and control data, and a payload cache to store the classified payload data, and a processing unit (PU) sub-system including a local PU cache to store the classified control data, wherein the payload cache and the local PU cache are different physical caches in respective different physical locations in the computer system, and processing core circuitry configured to execute software program instructions to perform control and packet processing responsively to the control data stored in the local PU cache.

公开(公告)号：US20210397560A1

公开(公告)日：2021-12-23

申请号：US16907347

申请日：2020-06-22

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Ilan Pardo ,  Hillel Chapman ,  Mark B. Rosenbluth

IPC: G06F12/0891 ,  G06F12/0817 ,  G06F12/0804 ,  G06F9/54 ,  H04L29/08 ,  H04L29/06

Abstract: In one embodiment, a computer server system includes a memory to store data across memory locations, multiple processing cores including respective local caches in which to cache cache-lines read from the memory, an interconnect to manage read and write operations of the memory and local caches, maintain local cache location data of the cached cache-lines according to respective ones of the memory locations from which the cached cache-lines were read from the memory, receive a write request for a data element to be written to one of the memory locations, find a local cache location in which to write the data element responsively to the local cache location data and the memory location of the write request, and send an update request to a first processing core to update a respective first local cache with the data element responsively to the found local cache location.

公开(公告)号：US11258887B2

公开(公告)日：2022-02-22

申请号：US16908776

申请日：2020-06-23

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Ilan Pardo ,  Mark B. Rosenbluth ,  Idan Burstein ,  Rui Xu ,  Oded Lempel ,  Tsofia Eshel

IPC: H04L29/06 ,  G06F12/0875 ,  G06F13/40 ,  H04L12/879 ,  H04L29/08 ,  H04L69/22 ,  H04L49/901 ,  H04L69/324 ,  H04L67/568

Abstract: In one embodiment, a computer system includes a payload sub-system including interfaces to connect with respective devices, transfer data with the respective devices, and receive write transactions from the respective devices, a classifier to classify the received write transactions into payload data and control data, and a payload cache to store the classified payload data, and a processing unit (PU) sub-system including a local PU cache to store the classified control data, wherein the payload cache and the local PU cache are different physical caches in respective different physical locations in the computer system, and processing core circuitry configured to execute software program instructions to perform control and packet processing responsively to the control data stored in the local PU cache.

公开(公告)号：US10942876B1

公开(公告)日：2021-03-09

申请号：US16683300

申请日：2019-11-14

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Carl Ramey ,  Christopher Jackson ,  Diane Orf ,  Matt Orsini ,  Michael Cotsford ,  Mark B. Rosenbluth ,  Rui Xu

IPC: G06F13/20 ,  G06F9/30 ,  G06F13/42

Abstract: One embodiment includes a computing device including peripheral component bus interfaces for connection to a peripheral component bus, a first integrated circuit (IC) chip comprising a processor to initiate a register setup process of the device, a second IC chip including a tile processor including multiple tiles, each tile including at least a processing core configured to generate requests to at least one of the peripheral component bus interfaces, steering configuration registers to store steering configuration data, and steering logic to steer the generated requests responsively to the steering configuration data in the steering configuration registers, and steering register setup circuitry including a multicaster and a register setup memory, wherein the processor is configured to write the steering configuration data to the register setup memory, and the multicaster is configured to multicast the steering configuration data written to the register setup memory to the steering configuration registers of the tiles.