公开(公告)号：US11558175B2

公开(公告)日：2023-01-17

申请号：US17233591

申请日：2021-04-19

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Miriam Menes ,  Noam Bloch ,  Adi Menachem ,  Idan Burstein ,  Ariel Shahar ,  Maxim Fudim

IPC: H04L9/06 ,  H04L9/08 ,  H04L9/32

Abstract: In one embodiment, data communication apparatus includes a network interface for connection to a network and configured to receive a sequence of data packets from a remote device over the network, the sequence including data blocks, ones of the data blocks having block boundaries that are not aligned with payload boundaries of the packets, and packet processing circuitry to cryptographically process the data blocks using a block cipher so as to write corresponding cryptographically processed data blocks to a memory, while holding segments of respective ones of the received data blocks in the memory, such that the packet processing circuitry stores a first segment of a data block of a first packet in the memory until a second packet is received, and then cryptographically processes the first and second segments together so as to write a corresponding cryptographically processed data block to the memory.

公开(公告)号：US11909856B2

公开(公告)日：2024-02-20

申请号：US18076423

申请日：2022-12-07

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Miriam Menes ,  Noam Bloch ,  Adi Menachem ,  Idan Burstein ,  Ariel Shahar ,  Maxim Fudim

IPC: H04L9/06 ,  H04L9/32 ,  H04L9/08

CPC classification number: H04L9/0625 ,  H04L9/0861 ,  H04L9/3247

Abstract: In one embodiment, an apparatus includes a network interface to receive a sequence of data packets from a remote device responsively to a data transfer request, the received sequence including received data blocks, and packet processing circuitry to read cryptographic parameters from a memory in which the parameters were registered by a processing unit, the cryptographic parameters including an initial cryptographic key and initial value, compute a first cryptographic key responsively to the initial cryptographic key and initial value, cryptographically process a first block responsively to the first cryptographic key, compute an updated value responsively to the initial value and a size of the first block, compute a second cryptographic key responsively to the initial cryptographic key and the updated value, cryptographically process a second block of the received data blocks responsively to the second cryptographic key, and write the cryptographically processed first and second block to the memory.

公开(公告)号：US11909855B2

公开(公告)日：2024-02-20

申请号：US18075460

申请日：2022-12-06

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Miriam Menes ,  Noam Bloch ,  Adi Menachem ,  Idan Burstein ,  Ariel Shahar ,  Maxim Fudim

IPC: H04L9/06 ,  H04L9/08 ,  H04L9/32

CPC classification number: H04L9/0625 ,  H04L9/0861 ,  H04L9/3247

Abstract: In one embodiment, data communication apparatus includes packet processing circuitry to receive data from a memory responsively to a data transfer request, and cryptographically process the received data in units of data blocks using a block cipher so as to add corresponding cryptographically processed data blocks to a sequence of data packets, the sequence including respective ones of the cryptographically processed data blocks having block boundaries that are not aligned with payload boundaries of respective one of the packets, such that respective ones of the cryptographically processed data blocks are divided into two respective segments, which are contained in successive respective ones of the packets in the sequence, and a network interface which includes one or more ports for connection to a packet data network and is configured to send the sequence of data packets to a remote device over the packet data network via the one or more ports.

公开(公告)号：US20200314181A1

公开(公告)日：2020-10-01

申请号：US16827912

申请日：2020-03-24

Applicant: Mellanox Technologies, Ltd.

Inventor： Haggai Eran ,  Dotan David Levi ,  Maxim Fudim ,  Liran Liss

IPC: H04L29/08

Abstract: A network node includes a bus switching element, and a network adapter, an accelerator and a host, all coupled to communicate via the bus switching element. The network adapter is configured to communicate with remote nodes over a communication network. The host is configured to establish a RDMA link between the accelerator and the RDMA endpoint by creating a Queue Pair (QP) to be used by the accelerator for communication with the RDMA endpoint via the RDMA link. The accelerator is configured to exchange data, via the network adapter, between a memory of the accelerator and a memory of the RDMA endpoint.

公开(公告)号：US20230097439A1

公开(公告)日：2023-03-30

申请号：US18075460

申请日：2022-12-06

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Miriam Menes ,  Noam Bloch ,  Adi Menachem ,  Idan Burstein ,  Ariel Shahar ,  Maxim Fudim

IPC: H04L9/06 ,  H04L9/08 ,  H04L9/32

Abstract: In one embodiment, data communication apparatus includes packet processing circuitry to receive data from a memory responsively to a data transfer request, and cryptographically process the received data in units of data blocks using a block cipher so as to add corresponding cryptographically processed data blocks to a sequence of data packets, the sequence including respective ones of the cryptographically processed data blocks having block boundaries that are not aligned with payload boundaries of respective one of the packets, such that respective ones of the cryptographically processed data blocks are divided into two respective segments, which are contained in successive respective ones of the packets in the sequence, and a network interface which includes one or more ports for connection to a packet data network and is configured to send the sequence of data packets to a remote device over the packet data network via the one or more ports.

公开(公告)号：US11184439B2

公开(公告)日：2021-11-23

申请号：US16827912

申请日：2020-03-24

Applicant: Mellanox Technologies, Ltd.

Inventor： Haggai Eran ,  Dotan David Levi ,  Maxim Fudim ,  Liran Liss

IPC: H04L29/08 ,  G06F13/28 ,  G06F15/173

Abstract: A network node includes a bus switching element, and a network adapter, an accelerator and a host, all coupled to communicate via the bus switching element. The network adapter is configured to communicate with remote nodes over a communication network. The host is configured to establish a RDMA link between the accelerator and the RDMA endpoint by creating a Queue Pair (QP) to be used by the accelerator for communication with the RDMA endpoint via the RDMA link. The accelerator is configured to exchange data, via the network adapter, between a memory of the accelerator and a memory of the RDMA endpoint.