-
公开(公告)号：US20230291409A1
公开(公告)日：2023-09-14
申请号：US17690063
申请日：2022-03-09
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Raanan Ivry
CPC classification number: H03L7/0994 , H02M1/0003 , H03M3/37
Abstract: An Integrated Circuit (IC) includes feedback control-loop (FCL) circuitry to generate a delay-compensated output signal responsively to an input reference signal. The FCL circuitry includes a main feedback path, a first subtractor, a delay-compensation feedback path, and a second subtractor. The main feedback path is to generate a main feedback signal responsively to the delay-compensated output signal. The first subtractor is to generate a non-compensated output signal responsively to a difference between the main feedback signal and the input reference signal. The delay-compensation feedback path is to generate a delay-compensation feedback signal responsively to the delay-compensated output signal. The second subtractor is to generate the delay-compensated output signal responsively to a difference between the non-compensated output signal and the delay-compensation feedback signal.
-
公开(公告)号：US10887077B1
公开(公告)日：2021-01-05
申请号：US16511746
申请日：2019-07-15
Applicant: Mellanox Technologies, Ltd.
Inventor： Raanan Ivry
Abstract: Embodiments are disclosed for timing recovery used in conjunction with a phase detector embedded in a receiver of a communication system. An example method includes receiving, via a receiver of a communication system, an input signal. The input signal encodes a plurality of bits in a number of amplitude levels. The method further includes using an analog to digital converter to generate a sampled signal based on the input signal. The method further includes using a first interpolation filter to filter the sampled signal. The method further includes using a second interpolation filter to filter the sampled signal. The method further includes using a first non-linear device to process an output of the first interpolation filter. The method further includes using a second non-linear device to process an output of the second interpolation filter. The method further includes performing a mathematical operation on an output of the first non-linear device with an output of the second non-linear device to generate phase information.
-
Patent Agency Ranking
公开(公告)号：US11502815B2
公开(公告)日：2022-11-15
申请号：US17189313
申请日：2021-03-02
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Hananel Faig , Raanan Ivry
Abstract: A signal processing method includes receiving a digital signal including a sequence of samples. For each sample among at least some of the samples, a neighbor-based estimate is calculated over (i) one or more samples that precede the sample in the sequence and (ii) one or more samples that succeed the sample in the sequence, and an error value, indicative of a deviation of the neighbor-based estimate from an actual value of the sample, is calculating. An impairment in the digital signal is estimated based on a plurality of error values calculated for a plurality of the samples.
-
公开(公告)号：US11967963B2
公开(公告)日：2024-04-23
申请号：US17690063
申请日：2022-03-09
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Raanan Ivry
CPC classification number: H03L7/0994 , H02M1/0003 , H03M3/37
Abstract: An Integrated Circuit (IC) includes feedback control-loop (FCL) circuitry to generate a delay-compensated output signal responsively to an input reference signal. The FCL circuitry includes a main feedback path, a first subtractor, a delay-compensation feedback path, and a second subtractor. The main feedback path is to generate a main feedback signal responsively to the delay-compensated output signal. The first subtractor is to generate a non-compensated output signal responsively to a difference between the main feedback signal and the input reference signal. The delay-compensation feedback path is to generate a delay-compensation feedback signal responsively to the delay-compensated output signal. The second subtractor is to generate the delay-compensated output signal responsively to a difference between the non-compensated output signal and the delay-compensation feedback signal.
-
公开(公告)号：US11757682B1
公开(公告)日：2023-09-12
申请号：US17731268
申请日：2022-04-28
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Raanan Ivry
CPC classification number: H04L25/03203 , H04B1/04 , H04L27/04 , H04L27/20 , H04L27/36
Abstract: A method for generating a Trellis-Coded Modulation (TCM) scheme for transmitting symbols over a Partial-Response (PR) channel, the method including holding a base TCM scheme including a plurality of states and transitions among the states. Sequences of symbols are produced, and second sequences of symbols are calculated, each second sequence emulating a response of the PR channel to a respective sequence of symbols traversing the PR channel. The TCM scheme is initialized by assigning the sequences to the transitions of the base TCM scheme. One or more transitions are removed so that second sequences corresponding to transitions that were not removed are separated by at least a first distance. One or more additional transitions are further removed from the TCM scheme, so that second sequences corresponding to parallel transitions from a current state to a next state are separated by at least a second distance larger than the first distance.
-
公开(公告)号：US20220286268A1
公开(公告)日：2022-09-08
申请号：US17189313
申请日：2021-03-02
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Hananel Faig , Raanan Ivry
Abstract: A signal processing method includes receiving a digital signal including a sequence of samples. For each sample among at least some of the samples, a neighbor-based estimate is calculated over (i) one or more samples that precede the sample in the sequence and (ii) one or more samples that succeed the sample in the sequence, and an error value, indicative of a deviation of the neighbor-based estimate from an actual value of the sample, is calculating. An impairment in the digital signal is estimated based on a plurality of error values calculated for a plurality of the samples.
-
公开(公告)号：US11070224B1
公开(公告)日：2021-07-20
申请号：US16868894
申请日：2020-05-07
Applicant: Mellanox Technologies, Ltd.
Inventor： Hananel Faig , Adam Kaminer , David (Dima) Rochlin , Raanan Ivry
Abstract: A method for providing back-compatibility for rational sampling rate disparities between two circuitries, comprises: a) providing a Phase Locked Loop (PLL) operating at a rate different than that of the Symbols generator, which is coupled to a Digital to Analog Converter (DAC) or an Analog to Digital Converter (ADC); b) providing an interpolation filter coupled to said converter, which filter is adapted to perform sampling rate conversion operations on the samples using zero-stuffing, filtering, and decimation, or the like computation-saving algorithm; and c) obtaining the sampling of the symbols at the required and compatible rate.
-
-
-
-
-
-
Search Results
7
records
(took 0.017 seconds)
