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    METHODS AND SYSTEMS FOR INTER-STACK COMMUNICATION FOR LOGICAL VOLUME MANAGEMENT
    1.
    发明公开
    METHODS AND SYSTEMS FOR INTER-STACK COMMUNICATION FOR LOGICAL VOLUME MANAGEMENT 审中-公开

    公开(公告)号：US20230236769A1

    公开(公告)日：2023-07-27

    申请号：US17586417

    申请日：2022-01-27

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Omri Kahalon ,  Gal Shalom ,  Aviad Yehezkel ,  Liran Liss ,  Oren Duer ,  Rabie Loulou ,  Maxim Gurtovoy

    IPC: G06F3/06

    CPC classification number: G06F3/0689 ,  G06F3/067 ,  G06F3/0631 ,  G06F3/0659 ,  G06F3/0613

    Abstract: Methods and systems provided herein involve extracting an input/output (I/O) operation from a packet received over an I/O pipeline, the I/O operation comprising either a read request to read data from at least one storage device or a write request to write data to the at least one storage device; determining that an address associated with the I/O operation exists in a lookup table that is provided for thin provisioning of the at least one storage device; performing one or more RAID calculations associated with the at least one storage device based on the address and the I/O operation; and accessing the at least one storage device to perform the I/O operation based on the one or more RAID calculations; and second processing component configured to carry out a second set of operations that occur when the address associated with the I/O operation does not exist in the lookup table.

    CONNECTOR MODULE WITH INTERNAL WIRELESS COMMUNICATION DEVICE
    2.
    发明申请
    CONNECTOR MODULE WITH INTERNAL WIRELESS COMMUNICATION DEVICE 有权
    具有内部无线通信设备的连接器模块

    公开(公告)号：US20160276784A1

    公开(公告)日：2016-09-22

    申请号：US14662258

    申请日：2015-03-19

    Applicant: Mellanox Technologies Ltd.

    Inventor： Sami Salloum ,  Rabie Loulou ,  Wasim Abu Moch

    IPC: H01R13/66

    CPC classification number: H01R13/6691 ,  H01R13/6658 ,  H01R29/00 ,  H04M1/7253 ,  H04M2250/04 ,  H04W88/02

    Abstract: A connector module includes a signal interface, a wireless communication module and a connector housing. The signal interface is configured to exchange signals between a cable and a communication unit when the connector module is connected to the communication unit. The wireless communication module is configured to exchange information in a first mode between the communication unit and a wireless terminal when the connector module is connected to the communication unit, and, when the connector module is disconnected from the communication unit, to exchange information in a second between a memory internal to the connector module and the wireless terminal mode. The connector housing contains the signal interface and the wireless communication module.

    Abstract translation: 连接器模块包括信号接口，无线通信模块和连接器壳体。 信号接口被配置为当连接器模块连接到通信单元时，在电缆和通信单元之间交换信号。 无线通信模块被配置为当连接器模块连接到通信单元时，在通信单元和无线终端之间以第一模式交换信息，并且当连接器模块与通信单元断开连接时，以交换信息 第二在连接器模块内部的存储器与无线终端模式之间。 连接器外壳包含信号接口和无线通信模块。

    SYSTEM WHICH PROVIDES PLURAL PROCESSES IN A HOST WITH ASYNCHRONOUS ACCESS TO PLURAL PORTIONS OF THE MEMORY OF ANOTHER HOST
    3.
    发明公开
    SYSTEM WHICH PROVIDES PLURAL PROCESSES IN A HOST WITH ASYNCHRONOUS ACCESS TO PLURAL PORTIONS OF THE MEMORY OF ANOTHER HOST 审中-公开

    公开(公告)号：US20230176769A1

    公开(公告)日：2023-06-08

    申请号：US17543334

    申请日：2021-12-06

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Gal Shalom ,  Adi Horowitz ,  Omri Kahalon ,  Liran Liss ,  Aviad Yehezkel ,  Rabie Loulou

    IPC: G06F3/06 ,  G06F9/54

    CPC classification number: G06F3/0655 ,  G06F9/544 ,  G06F3/061 ,  G06F3/0673

    Abstract: API in conjunction with a bridge chip and first and second hosts having first and second memories respectively. The bridge chip connects the memories. The API comprises key identifier registration functionality to register a key identifier for each of plural computer processes performed by the first host, thereby to define plural key identifiers; and/or access control functionality to provide at least computer process P1 performed by the first host with access, typically via the bridge chip, to at least local memory buffer M2 residing in the second memory, typically after the access control functionality first validates that process P1 has a key identifier which has been registered, e.g., via the key identifier registration functionality. Typically, the access control functionality also prevents at least computer process P2, performed by the first host, which has not registered a key identifier, from accessing local memory buffer M2, e.g., via the bridge chip.

    Methods and systems for inter-stack communication for logical volume management
    5.
    发明授权
    Methods and systems for inter-stack communication for logical volume management 有权

    公开(公告)号：US12147716B2

    公开(公告)日：2024-11-19

    申请号：US17586417

    申请日：2022-01-27

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Omri Kahalon ,  Gal Shalom ,  Aviad Yehezkel ,  Liran Liss ,  Oren Duer ,  Rabie Loulou ,  Maxim Gurtovoy

    IPC: G06F3/00 ,  G06F3/06

    Abstract: Methods and systems provided herein involve extracting an input/output (I/O) operation from a packet received over an I/O pipeline, the I/O operation comprising either a read request to read data from at least one storage device or a write request to write data to the at least one storage device; determining that an address associated with the I/O operation exists in a lookup table that is provided for thin provisioning of the at least one storage device; performing one or more RAID calculations associated with the at least one storage device based on the address and the I/O operation; and accessing the at least one storage device to perform the I/O operation based on the one or more RAID calculations; and second processing component configured to carry out a second set of operations that occur when the address associated with the I/O operation does not exist in the lookup table.

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