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    METHODS AND SYSTEMS FOR INTER-STACK COMMUNICATION FOR LOGICAL VOLUME MANAGEMENT
    2.
    发明公开
    METHODS AND SYSTEMS FOR INTER-STACK COMMUNICATION FOR LOGICAL VOLUME MANAGEMENT 审中-公开

    公开(公告)号：US20230236769A1

    公开(公告)日：2023-07-27

    申请号：US17586417

    申请日：2022-01-27

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Omri Kahalon ,  Gal Shalom ,  Aviad Yehezkel ,  Liran Liss ,  Oren Duer ,  Rabie Loulou ,  Maxim Gurtovoy

    IPC: G06F3/06

    CPC classification number: G06F3/0689 ,  G06F3/067 ,  G06F3/0631 ,  G06F3/0659 ,  G06F3/0613

    Abstract: Methods and systems provided herein involve extracting an input/output (I/O) operation from a packet received over an I/O pipeline, the I/O operation comprising either a read request to read data from at least one storage device or a write request to write data to the at least one storage device; determining that an address associated with the I/O operation exists in a lookup table that is provided for thin provisioning of the at least one storage device; performing one or more RAID calculations associated with the at least one storage device based on the address and the I/O operation; and accessing the at least one storage device to perform the I/O operation based on the one or more RAID calculations; and second processing component configured to carry out a second set of operations that occur when the address associated with the I/O operation does not exist in the lookup table.

    Interrupt emulation on network devices
    4.
    发明授权
    Interrupt emulation on network devices 有权

    公开(公告)号：US12174765B2

    公开(公告)日：2024-12-24

    申请号：US17707555

    申请日：2022-03-29

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Daniel Marcovitch ,  Liran Liss ,  Rabia Loulou ,  Aviad Yehezkel

    IPC: G06F13/24 ,  G06F13/40 ,  G06F13/42 ,  G06F15/173

    Abstract: Methods, systems, and devices for message signaled interrupt (MSI-X) tunneling on a host device exposed by a bridge connection are described. A device may receive data and a first interrupt signal from a remote destination over a network protocol. The device may receive the data and/or the first interrupt signal over the bridge connection, via a tunneled communication from the remote destination. The device may generate a second interrupt signal based on the first interrupt signal and a local interrupt configuration provided by a system bus driver of the device. The device may inject the data and the second interrupt signal over the system bus. Injecting the data and injecting the second interrupt signal may include ensuring the data is made available to the system bus driver, prior to the interrupt handler receiving the second interrupt signal.

    SYSTEM WHICH PROVIDES PLURAL PROCESSES IN A HOST WITH ASYNCHRONOUS ACCESS TO PLURAL PORTIONS OF THE MEMORY OF ANOTHER HOST
    6.
    发明公开
    SYSTEM WHICH PROVIDES PLURAL PROCESSES IN A HOST WITH ASYNCHRONOUS ACCESS TO PLURAL PORTIONS OF THE MEMORY OF ANOTHER HOST 审中-公开

    公开(公告)号：US20230176769A1

    公开(公告)日：2023-06-08

    申请号：US17543334

    申请日：2021-12-06

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Gal Shalom ,  Adi Horowitz ,  Omri Kahalon ,  Liran Liss ,  Aviad Yehezkel ,  Rabie Loulou

    IPC: G06F3/06 ,  G06F9/54

    CPC classification number: G06F3/0655 ,  G06F9/544 ,  G06F3/061 ,  G06F3/0673

    Abstract: API in conjunction with a bridge chip and first and second hosts having first and second memories respectively. The bridge chip connects the memories. The API comprises key identifier registration functionality to register a key identifier for each of plural computer processes performed by the first host, thereby to define plural key identifiers; and/or access control functionality to provide at least computer process P1 performed by the first host with access, typically via the bridge chip, to at least local memory buffer M2 residing in the second memory, typically after the access control functionality first validates that process P1 has a key identifier which has been registered, e.g., via the key identifier registration functionality. Typically, the access control functionality also prevents at least computer process P2, performed by the first host, which has not registered a key identifier, from accessing local memory buffer M2, e.g., via the bridge chip.

    SESSION SHARING WITH REMOTE DIRECT MEMORY ACCESS CONNECTIONS
    7.
    发明申请
    SESSION SHARING WITH REMOTE DIRECT MEMORY ACCESS CONNECTIONS 有权

    公开(公告)号：US20250141961A1

    公开(公告)日：2025-05-01

    申请号：US19012523

    申请日：2025-01-07

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Adi Merav Horowitz ,  Rabia Loulou ,  Omri Kahalon ,  Gal Shalom ,  Aviad Yehezkel ,  Asaf Schwartz ,  Liran Liss

    IPC: H04L67/1097 ,  H04L67/146

    Abstract: Systems and methods enable session sharing for session-based remote direct memory access (RDMA). Multiple queue pairs (QPs) can be added to a single session and/or session group where each of the QPs has a common remote. Systems and methods may query a session ID for an existing session group and then use the session ID with an add QP request to join additional QPs to an existing session. Newly added QPs may share one or more features with existing QPs of the session group, such as encryption parameters. Additionally, newly added QPs may be configured with different performance or quality of service requirements, thereby isolating performance, and permitting true scaling for high performance computing applications.

    INTERRUPT EMULATION ON NETWORK DEVICES
    8.
    发明申请
    INTERRUPT EMULATION ON NETWORK DEVICES 有权

    公开(公告)号：US20250123980A1

    公开(公告)日：2025-04-17

    申请号：US18988345

    申请日：2024-12-19

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Daniel Marcovitch ,  Liran Liss ,  Rabia Loulou ,  Aviad Yehezkel

    IPC: G06F13/24 ,  G06F13/40 ,  G06F13/42 ,  G06F15/173

    Abstract: Methods, systems, and devices for message signaled interrupt (MSI-X) tunneling on a host device exposed by a bridge connection are described. A device may receive data and a first interrupt signal from a remote destination over a network protocol. The device may receive the data and/or the first interrupt signal over the bridge connection, via a tunneled communication from the remote destination. The device may generate a second interrupt signal based on the first interrupt signal and a local interrupt configuration provided by a system bus driver of the device. The device may inject the data and the second interrupt signal over the system bus. Injecting the data and injecting the second interrupt signal may include ensuring the data is made available to the system bus driver, prior to the interrupt handler receiving the second interrupt signal.

    LINK AGGREGATION IN INFINIBAND NETWORKS
    9.
    发明公开
    LINK AGGREGATION IN INFINIBAND NETWORKS 审中-公开

    公开(公告)号：US20240259298A1

    公开(公告)日：2024-08-01

    申请号：US18162174

    申请日：2023-01-31

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Adi Horowitz ,  Omri Kahalon ,  Gal Shalom ,  Rabia Loulou ,  Aviad Yehezkel ,  Matty Kadosh

    IPC: H04L45/24 ,  H04L61/103

    CPC classification number: H04L45/245 ,  H04L61/103 ,  H04L2101/668

    Abstract: Systems and methods herein are for one or more processing units of a subnet manger (SM) to communicate configuration information with at least one subnet management agent (SMA) that is associated with at least one switch and with a host machine, the configuration information to enable the at least one switch to configure a forwarding table based in part on a mapping of at least one virtual network address to physical network addresses of two or more physical ports of the host machine, and the configuration information to enable the host machine to communicate with other host machines using the at least one switch and the at least one virtual network address.

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