公开(公告)号：US11575594B2

公开(公告)日：2023-02-07

申请号：US17016464

申请日：2020-09-10

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Jose Yallouz ,  Lion Levi ,  Tamir Ronen ,  Vladimir Koushnir ,  Neria Uzan

IPC: G06F15/16 ,  H04L45/00 ,  H04L41/12 ,  H04L45/48 ,  H04L12/44

Abstract: A computing system including network elements arranged in at least one group. A plurality of the network elements are designated as spines and another plurality are designated as leaves, the spines and leaves are interconnected in a bipartite topology, and at least some of the spines and leaves are configured to: receive in a first leaf, from a source node, packets destined to a destination node via a second leaf, forward the packets via a first link to a first spine and to the second leaf via a second link, in response to detecting that the second link has failed, apply a detour path from the first leaf to the second leaf, including a detour link in a spine-to-leaf direction and another detour link a leaf-to-spine direction, and forward subsequent packets, which are received in the first leaf and are destined to the second leaf, via the detour path.

公开(公告)号：US11552882B2

公开(公告)日：2023-01-10

申请号：US17211904

申请日：2021-03-25

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Jose Yallouz ,  Lion Levi ,  Gil Mey-Tal ,  Daniel Klein

IPC: H04L12/703 ,  H04L12/721 ,  H04L12/707 ,  H04L12/717 ,  H04L45/28 ,  H04L45/42 ,  H04L45/00 ,  H04L45/12

Abstract: A network element includes processing circuitry and multiple ports. The ports connect using links to a communication network. The processing circuitry is configured to receive packets via the ports and forward the received packets to respective destination addresses via the ports. The destination addresses are organized in address groups, each address group including multiple destination addresses of nodes connected to a common network element in the communication network. The processing circuitry is further configured to, in response to identifying that a given port connects to a faulty link, determine one or more address groups that became unreachable via the given port due to the faulty link, generate a notification reporting one or more of the determined address groups that are unreachable via any port other than the given port, and transmit the notification to one or more other network elements, via one or more ports other than the given port.

公开(公告)号：US20220311702A1

公开(公告)日：2022-09-29

申请号：US17211904

申请日：2021-03-25

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Jose Yallouz ,  Lion Levi ,  Gil Mey-Tal ,  Daniel Klein

IPC: H04L12/703 ,  H04L12/721 ,  H04L12/707 ,  H04L12/717

Abstract: A network element includes processing circuitry and multiple ports. The ports connect using links to a communication network. The processing circuitry is configured to receive packets via the ports and forward the received packets to respective destination addresses via the ports. The destination addresses are organized in address groups, each address group including multiple destination addresses of nodes connected to a common network element in the communication network. The processing circuitry is further configured to, in response to identifying that a given port connects to a faulty link, determine one or more address groups that became unreachable via the given port due to the faulty link, generate a notification reporting one or more of the determined address groups that are unreachable via any port other than the given port, and transmit the notification to one or more other network elements, via one or more ports other than the given port.

公开(公告)号：US11425027B2

公开(公告)日：2022-08-23

申请号：US17086412

申请日：2020-11-01

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Michael Gandelman ,  Jose Yallouz ,  Lion Levi ,  Tamir Ronen ,  Aviad Levy ,  Vladimir Koushnir

IPC: H04L45/00 ,  H04L45/02 ,  H04L45/122 ,  H04L49/00

Abstract: An apparatus includes an interface and a processor. The interface communicates with a network including network elements interconnected in a Cartesian topology. The processor defines first and second groups of turns, each turn includes a hop from a previous network element to a current network element and a hop from the current network element to a next network element. Based on the turns, the processor specifies rules that when applied to packets traversing respective network elements, guarantee that no deadlock conditions occur in the network. The rules for a given network element include (i) forwarding rules to reach a given target without traversing the turns of the second group, and (ii) Virtual Lane (VL) modification rules for reassigning packets, which traverse turns of the first group and which are assigned to a first VL, to a different second VL. The processor configures the given network element with the rules.

公开(公告)号：US20220174000A1

公开(公告)日：2022-06-02

申请号：US17108269

申请日：2020-12-01

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Gal Mendelson ,  Jose Yallouz

IPC: H04L12/707 ,  H04L12/721 ,  H04L12/773

Abstract: A switch, communication system, and method are provided. In one example, a communication system is described that includes a plurality of communication nodes and a switch that interconnects and facilitates a transmission of packets between the plurality of communication nodes. The communication system may be configured such that the packets are transmitted between the plurality of communication nodes by draining a demand matrix.

公开(公告)号：US20220141125A1

公开(公告)日：2022-05-05

申请号：US17086412

申请日：2020-11-01

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Michael Gandelman ,  Jose Yallouz ,  Lion Levi ,  Tamir Ronen ,  Aviad Levy ,  Vladimir Koushnir

IPC: H04L12/733 ,  H04L12/751 ,  H04L12/721 ,  H04L12/707 ,  H04L12/935

Abstract: An apparatus includes an interface and a processor. The interface communicates with a network including network elements interconnected in a Cartesian topology. The processor defines first and second groups of turns, each turn includes a hop from a previous network element to a current network element and a hop from the current network element to a next network element. Based on the turns, the processor specifies rules that when applied to packets traversing respective network elements, guarantee that no deadlock conditions occur in the network. The rules for a given network element include (i) forwarding rules to reach a given target without traversing the turns of the second group, and (ii) Virtual Lane (VL) modification rules for reassigning packets, which traverse turns of the first group and which are assigned to a first VL, to a different second VL. The processor configures the given network element with the rules.

公开(公告)号：US20220078104A1

公开(公告)日：2022-03-10

申请号：US17016464

申请日：2020-09-10

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Jose Yallouz ,  Lion Levi ,  Tamir Ronen ,  Vladimir Koushnir ,  Neria Uzan

IPC: H04L12/707 ,  H04L12/44 ,  H04L12/753 ,  H04L12/24

Abstract: A computing system including network elements arranged in at least one group. A plurality of the network elements are designated as spines and another plurality are designated as leaves, the spines and leaves are interconnected in a bipartite topology, and at least some of the spines and leaves are configured to: receive in a first leaf, from a source node, packets destined to a destination node via a second leaf, forward the packets via a first link to a first spine and to the second leaf via a second link, in response to detecting that the second link has failed, apply a detour path from the first leaf to the second leaf, including a detour link in a spine-to-leaf direction and another detour link a leaf-to-spine direction, and forward subsequent packets, which are received in the first leaf and are destined to the second leaf, via the detour path.