公开(公告)号：US11909848B2

公开(公告)日：2024-02-20

申请号：US16924221

申请日：2020-07-09

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： David Pilnik ,  Yair Chasdai ,  Liran Daniel

IPC: H04L69/04 ,  H04L49/00

CPC classification number: H04L69/04 ,  H04L49/3063 ,  H04L2212/00

Abstract: In one embodiment, a device includes a data compression engine configured to process data packets of multiple network flows received from a network, and compress respective groups of the received data packets into respective compressed packets for sending over the network, each respective compressed packet including respective ones of the received data packets from different ones of the network flows, wherein the network interface is configured to send the compressed packets over the network.

公开(公告)号：US11770326B2

公开(公告)日：2023-09-26

申请号：US17368871

申请日：2021-07-07

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Tamir Ronen ,  Yuval Shpigelman

IPC: H04L45/122 ,  G06F13/40 ,  H04L45/02 ,  H04L45/00 ,  H04L45/586

CPC classification number: H04L45/122 ,  G06F13/4036 ,  H04L45/02 ,  H04L45/22 ,  H04L45/38 ,  H04L45/586

Abstract: An apparatus includes a network interface and a processor. The network interface communicates with a network including switches interconnected in a Cartesian topology having multiple dimensions. The processor predefines turn types of turns in the Cartesian topology, each turn traverses first and second hops along first and second dimensions having same or different respective identities, and each turn type is defined at least by identities of the first and second dimensions. The processor searches for a preferred route from a source switch to a destination switch, by evaluating candidate routes based on the number of VLs required for preventing a deadlock condition caused by the candidate route. The number of VLs required depends on a sequential pattern of turn types formed by the candidate route. The processor configures one or more switches in the network to route packets from the source switch to the destination switch along the preferred route.

公开(公告)号：US11709321B2

公开(公告)日：2023-07-25

申请号：US17503314

申请日：2021-10-17

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Henning Lysdal ,  Barak Gafni

IPC: G02B6/35 ,  F21V8/00 ,  H04J14/02

CPC classification number: G02B6/3548 ,  G02B6/0026 ,  H04J14/0209

Abstract: An optical cable includes a single optical connector configured for insertion into an optical receptacle so as to receive optical signals at a plurality of different wavelengths from the optical receptacle, and multiple electrical connectors, configured for insertion into respective electrical receptacles. Each electrical connector includes a transceiver configured to convert the optical signals into electrical output signals for output to an electrical receptacle. The optical cable further includes a plurality of optical fibers, having respective first ends connected together to the single optical connector so as to receive the optical signals. Each of the optical fibers has a respective second end coupled to a respective one of the electrical connectors. Wavelength selection optics are associated with the optical fibers so that the transceiver in each of the electrical connectors receives the optical signals at a different, respective one of the wavelengths.

公开(公告)号：US11546264B2

公开(公告)日：2023-01-03

申请号：US17204982

申请日：2021-03-18

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Roni Bar Yanai ,  Eliezer Britstein ,  Guy Twaig

IPC: H04L47/2408 ,  H04L47/26 ,  H04L47/34 ,  H04L47/2441

Abstract: A network device includes one or more communication ports, a packet processing circuit and an activity evaluation circuit. The one or more communication ports are configured to communicate packets over a network. The packet processing circuit is configured to process the packets. The activity evaluation circuit is configured to generate a sequence of multiple evaluation times independently of the packets, and, for each evaluation time among at least some of the evaluation times in the sequence, for any packet that is processed by the packet processing circuit at the evaluation time, to identify a session to which the packet belongs and issue an increment event associated with the identified session.

公开(公告)号：US20220353174A1

公开(公告)日：2022-11-03

申请号：US17246736

申请日：2021-05-03

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Aviv Kfir ,  Barak Gafni ,  Ilya Vershkov

IPC: H04L12/707 ,  H04L12/721

Abstract: A network device includes processing circuitry and multiple ports. The multiple ports are configured to connect to a communication network. The processing circuitry is configured to select a first port among the multiple ports to serve as an egress port for a packet, and to forward the packet to the first port, irrespective of whether or not the first port is usable as the egress port. The processing circuitry is further configured to, when the first port is usable as the egress port, transmit the packet to the communication network via the first port, and when the first port is unusable as the egress port, forward the packet from the first port to a second port among the multiple ports and transmit the packet to the communication network via the second port.

公开(公告)号：US20220294717A1

公开(公告)日：2022-09-15

申请号：US17198298

申请日：2021-03-11

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Alan Lo ,  Matty Kadosh ,  Marian Pritsak ,  Yonatan Piasetsky

IPC: H04L12/26 ,  H04W24/08

Abstract: In one embodiment, a system includes a first data communication device including packet processing circuitry to provide a probe packet including an egress timestamp TS1 indicating a time at which the probe packet egresses the first data communication device, and a network interface to send the probe packet via at least one network connection to a second data communication device, and receive from the second data communication device a response packet including the egress timestamp TS1, wherein the packet processing circuitry is configured to associate with the response packet an ingress timestamp TS2 indicating a time at which the response packet ingresses the first data communication device, and a network metric processor to compute a data latency in the at least one network connection responsively to TS1, TS2, and an indication of an internal latency of the probe packet in the second data communication device.

公开(公告)号：US11411911B2

公开(公告)日：2022-08-09

申请号：US17079543

申请日：2020-10-26

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Lion Levi ,  Vladimir Koushnir ,  Matty Kadosh ,  Gil Bloch ,  Aviad Levy ,  Liran Liss ,  Dvir Libhaber

IPC: H04L61/103 ,  H04L45/02

Abstract: A router includes routing circuitry and a plurality of ports. The routing circuitry is configured to receive from a first subnetwork, via one of the ports, a packet destined to be delivered to a target node located in a second subnetwork, to select a mapping, from among two or more mappings, depending on a topological relation between the first subnetwork and the second subnetwork, to map a Layer-3 address of the packet into a Layer-2 address using the selected mapping, and to forward the packet via another one of the ports to the Layer-2 address.

公开(公告)号：US20220174000A1

公开(公告)日：2022-06-02

申请号：US17108269

申请日：2020-12-01

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Gal Mendelson ,  Jose Yallouz

IPC: H04L12/707 ,  H04L12/721 ,  H04L12/773

Abstract: A switch, communication system, and method are provided. In one example, a communication system is described that includes a plurality of communication nodes and a switch that interconnects and facilitates a transmission of packets between the plurality of communication nodes. The communication system may be configured such that the packets are transmitted between the plurality of communication nodes by draining a demand matrix.

公开(公告)号：US20220146767A1

公开(公告)日：2022-05-12

申请号：US17117867

申请日：2020-12-10

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Elad Mentovich ,  Yaakov Gridish ,  Anna Sandomirsky ,  Alon Rubinstein ,  Nimrod Rockman ,  Dimitrios Kalavrouziotis

IPC: G02B6/42 ,  H04B10/40 ,  H04B10/25

Abstract: A package includes a light emitting portion configured to emit light, a lens including a first lens surface and a second lens surface, a protective layer between the light emitting portion and the first lens surface and that shields the first lens surface from a surrounding environment, and an optical component that redirects light output from the second lens surface. The first lens surface is configured to receive the emitted light from the light emitting portion, the second lens surface is configured output light that has passed through the first lens surface, and the protective layer has a refractive index greater than 1.5.

公开(公告)号：US20220141125A1

公开(公告)日：2022-05-05

申请号：US17086412

申请日：2020-11-01

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Michael Gandelman ,  Jose Yallouz ,  Lion Levi ,  Tamir Ronen ,  Aviad Levy ,  Vladimir Koushnir

IPC: H04L12/733 ,  H04L12/751 ,  H04L12/721 ,  H04L12/707 ,  H04L12/935

Abstract: An apparatus includes an interface and a processor. The interface communicates with a network including network elements interconnected in a Cartesian topology. The processor defines first and second groups of turns, each turn includes a hop from a previous network element to a current network element and a hop from the current network element to a next network element. Based on the turns, the processor specifies rules that when applied to packets traversing respective network elements, guarantee that no deadlock conditions occur in the network. The rules for a given network element include (i) forwarding rules to reach a given target without traversing the turns of the second group, and (ii) Virtual Lane (VL) modification rules for reassigning packets, which traverse turns of the first group and which are assigned to a first VL, to a different second VL. The processor configures the given network element with the rules.