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公开(公告)号：US20220029854A1
公开(公告)日：2022-01-27
申请号：US17495824
申请日：2021-10-07
Applicant: MELLANOX TECHNOLOGIES TLV LTD.
Inventor： Richard Graham , Lion Levi , Gil Bloch , Daniel Marcovitch , Noam Bloch , Yong Qin , Yaniv Blumenfeld , Eitan Zahavi
Abstract: A method in which a plurality of process are configured to hold a block of data destined for other processes, with data repacking circuitry including receiving circuitry configured to receive at least one block of data from a source process of the plurality of processes, the repacking circuitry configured to repack received data in accordance with at least one destination process of the plurality of processes, and sending circuitry configured to send the repacked data to the at least one destination process of the plurality of processes, receiving a set of data for all-to-all data exchange, the set of data being configured as a matrix, the matrix being distributed among the plurality of processes, and transposing the data by each of the plurality of processes sending matrix data from the process to the repacking circuitry, and the repacking circuitry receiving, repacking, and sending the resulting matrix data to destination processes.
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公开(公告)号：US20200265043A1
公开(公告)日：2020-08-20
申请号：US16782118
申请日：2020-02-05
Applicant: MELLANOX TECHNOLOGIES TLV LTD.
Inventor： Richard Graham , Lion Levi
IPC: G06F16/242 , G06F16/22 , G06F16/21
Abstract: A method including providing a SHARP tree including a plurality of data receiving processes and at least one aggregation node, designating a data movement command, providing a plurality of data input vectors to each of the plurality of data receiving processes, respectively, the plurality of data receiving processes each passing on the respective received data input vector to the at least one aggregation node, and the at least one aggregation node carrying out the data movement command on the received plurality of data input vectors. Related apparatus and methods are also provided.
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公开(公告)号：US10419329B2
公开(公告)日：2019-09-17
申请号：US15473643
申请日：2017-03-30
Applicant: Mellanox Technologies TLV Ltd.
Inventor： Lion Levi , George Elias , Oded Wertheim , Amiad Marelli , Miriam Menes , Itamar Rabenstein , Noam Avital , Evyatar Romlet , Ofir Merdler
IPC: H04L12/761 , H04L1/16
Abstract: Communication apparatus includes a plurality of interfaces for receiving and transmitting data packets from and to a network and a memory, which receives and stores context data with respect to multicast groups. Packet processing circuitry establishes reliable connections over the network with the receiving nodes in the multicast groups, and upon receiving from a packet source on the network an incoming unicast packet containing multicast data and containing multicast metadata that identifies a multicast group, sends an acknowledgment of the incoming unicast packet to the packet source, reads the context data from the memory with respect to the identified multicast group, and transmits multiple outgoing unicast packets containing the multicast data via respective egress interfaces to the receiving nodes in the multicast group over the reliable connections.
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公开(公告)号：US20180287928A1
公开(公告)日：2018-10-04
申请号：US15473643
申请日：2017-03-30
Applicant: Mellanox Technologies TLV Ltd.
Inventor： Lion Levi , George Elias , Oded Wertheim , Amiad Marelli , Miriam Menes , Itamar Rabenstein , Noam Avital , Evyatar Romlet , Ofir Merdler
IPC: H04L12/761
CPC classification number: H04L45/16 , H04L1/16 , H04L1/1835 , H04L1/188 , H04L2001/0093
Abstract: Communication apparatus includes a plurality of interfaces for receiving and transmitting data packets from and to a network and a memory, which receives and stores context data with respect to multicast groups. Packet processing circuitry establishes reliable connections over the network with the receiving nodes in the multicast groups, and upon receiving from a packet source on the network an incoming unicast packet containing multicast data and containing multicast metadata that identifies a multicast group, sends an acknowledgment of the incoming unicast packet to the packet source, reads the context data from the memory with respect to the identified multicast group, and transmits multiple outgoing unicast packets containing the multicast data via respective egress interfaces to the receiving nodes in the multicast group over the reliable connections.
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公开(公告)号：US11411911B2
公开(公告)日：2022-08-09
申请号：US17079543
申请日：2020-10-26
Applicant: Mellanox Technologies TLV Ltd.
Inventor： Lion Levi , Vladimir Koushnir , Matty Kadosh , Gil Bloch , Aviad Levy , Liran Liss , Dvir Libhaber
IPC: H04L61/103 , H04L45/02
Abstract: A router includes routing circuitry and a plurality of ports. The routing circuitry is configured to receive from a first subnetwork, via one of the ports, a packet destined to be delivered to a target node located in a second subnetwork, to select a mapping, from among two or more mappings, depending on a topological relation between the first subnetwork and the second subnetwork, to map a Layer-3 address of the packet into a Layer-2 address using the selected mapping, and to forward the packet via another one of the ports to the Layer-2 address.
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Patent Agency Ranking
公开(公告)号：US20220141125A1
公开(公告)日：2022-05-05
申请号：US17086412
申请日：2020-11-01
Applicant: MELLANOX TECHNOLOGIES TLV LTD.
Inventor： Michael Gandelman , Jose Yallouz , Lion Levi , Tamir Ronen , Aviad Levy , Vladimir Koushnir
IPC: H04L12/733 , H04L12/751 , H04L12/721 , H04L12/707 , H04L12/935
Abstract: An apparatus includes an interface and a processor. The interface communicates with a network including network elements interconnected in a Cartesian topology. The processor defines first and second groups of turns, each turn includes a hop from a previous network element to a current network element and a hop from the current network element to a next network element. Based on the turns, the processor specifies rules that when applied to packets traversing respective network elements, guarantee that no deadlock conditions occur in the network. The rules for a given network element include (i) forwarding rules to reach a given target without traversing the turns of the second group, and (ii) Virtual Lane (VL) modification rules for reassigning packets, which traverse turns of the first group and which are assigned to a first VL, to a different second VL. The processor configures the given network element with the rules.
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公开(公告)号：US20220078104A1
公开(公告)日：2022-03-10
申请号：US17016464
申请日：2020-09-10
Applicant: MELLANOX TECHNOLOGIES TLV LTD.
Inventor： Jose Yallouz , Lion Levi , Tamir Ronen , Vladimir Koushnir , Neria Uzan
IPC: H04L12/707 , H04L12/44 , H04L12/753 , H04L12/24
Abstract: A computing system including network elements arranged in at least one group. A plurality of the network elements are designated as spines and another plurality are designated as leaves, the spines and leaves are interconnected in a bipartite topology, and at least some of the spines and leaves are configured to: receive in a first leaf, from a source node, packets destined to a destination node via a second leaf, forward the packets via a first link to a first spine and to the second leaf via a second link, in response to detecting that the second link has failed, apply a detour path from the first leaf to the second leaf, including a detour link in a spine-to-leaf direction and another detour link a leaf-to-spine direction, and forward subsequent packets, which are received in the first leaf and are destined to the second leaf, via the detour path.
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公开(公告)号：US20210042251A1
公开(公告)日：2021-02-11
申请号：US16537576
申请日：2019-08-11
Applicant: MELLANOX TECHNOLOGIES TLV LTD.
Inventor： Lion Levi , Aviv Kfir , Idan Matari , Ran Shani , Zachy Haramaty , Nir Monovich , Matty Kadosh
IPC: G06F13/28 , G06F13/40 , H04L12/861 , H04L12/725
Abstract: A network element includes one or more ports for communicating over a network, a processor and packet processing hardware. The packet processing hardware is configured to transfer packets to and from the ports, and further includes data-transfer circuitry for data transfer with the processor. The processor and the data-transfer circuitry are configured to transfer between one another (i) one or more communication packets for transferal between the ports and the processor and (ii) one or more databases for transferal between the packet processing hardware and the processor, by (i) translating, by the processor, the transferal of both the communication packets and the databases into work elements, and posting the work elements on one or more work queues in a memory of the processor, and (ii) using the data-transfer circuitry, executing the work elements so as to transfer both the communication packets and the databases.
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公开(公告)号：US20200274733A1
公开(公告)日：2020-08-27
申请号：US16789458
申请日：2020-02-13
Applicant: MELLANOX TECHNOLOGIES TLV LTD.
Inventor： Richard Graham , Lion Levi , Gil Bloch , Daniel Marcovitch , Noam Bloch , Yong Qin , Yaniv Blumenfeld , Eitan Zahavi
Abstract: A method in which a plurality of process are configured to hold a block of data destined for other processes, with data repacking circuitry including receiving circuitry configured to receive at least one block of data from a source process of the plurality of processes, the repacking circuitry configured to repack received data in accordance with at least one destination process of the plurality of processes, and sending circuitry configured to send the repacked data to the at least one destination process of the plurality of processes, receiving a set of data for all-to-all data exchange, the set of data being configured as a matrix, the matrix being distributed among the plurality of processes, and transposing the data by each of the plurality of processes sending matrix data from the process to the repacking circuitry, and the repacking circuitry receiving, repacking, and sending the resulting matrix data to destination processes.
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公开(公告)号：US11876642B2
公开(公告)日：2024-01-16
申请号：US17495824
申请日：2021-10-07
Applicant: MELLANOX TECHNOLOGIES TLV LTD.
Inventor： Richard Graham , Lion Levi , Gil Bloch , Daniel Marcovitch , Noam Bloch , Yong Qin , Yaniv Blumenfeld , Eitan Zahavi
CPC classification number: H04L12/40182 , G06F12/0246 , H04B7/0456 , H04L12/44 , H04W24/10 , H04W88/06
Abstract: A method in which a plurality of process are configured to hold a block of data destined for other processes, with data repacking circuitry including receiving circuitry configured to receive at least one block of data from a source process of the plurality of processes, the repacking circuitry configured to repack received data in accordance with at least one destination process of the plurality of processes, and sending circuitry configured to send the repacked data to the at least one destination process of the plurality of processes, receiving a set of data for all-to-all data exchange, the set of data being configured as a matrix, the matrix being distributed among the plurality of processes, and transposing the data by each of the plurality of processes sending matrix data from the process to the repacking circuitry, and the repacking circuitry receiving, repacking, and sending the resulting matrix data to destination processes.
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