公开(公告)号：US20220131826A1

公开(公告)日：2022-04-28

申请号：US17079543

申请日：2020-10-26

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Lion Levi ,  Vladimir Koushnir ,  Matty Kadosh ,  Gil Bloch ,  Aviad Levy ,  Liran Liss ,  Dvir Libhaber

IPC: H04L29/12 ,  H04L12/751

Abstract: A router includes routing circuitry and a plurality of ports. The routing circuitry is configured to receive from a first subnetwork, via one of the ports, a packet destined to be delivered to a target node located in a second subnetwork, to select a mapping, from among two or more mappings, depending on a topological relation between the first subnetwork and the second subnetwork, to map a Layer-3 address of the packet into a Layer-2 address using the selected mapping, and to forward the packet via another one of the ports to the Layer-2 address.

公开(公告)号：US20210218808A1

公开(公告)日：2021-07-15

申请号：US17147487

申请日：2021-01-13

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Richard Graham ,  Lion Levi ,  Daniel Marcovitch ,  Larry R. Dennison ,  Aviad Levy ,  Noam Bloch ,  Gil Bloch

IPC: H04L29/08

Abstract: An apparatus includes one or more ports for connecting to a communication network, processing circuitry and a message aggregation circuit (MAC). The processing circuitry is configured to communicate messages over the communication network via the one or more ports. The MAC is configured to receive messages, which originate in one or more source processes and are destined to one or more destination processes, to aggregate two or more of the messages that share a common destination into an aggregated message, and to send the aggregated message using the processing circuitry over the communication network.

公开(公告)号：US11750699B2

公开(公告)日：2023-09-05

申请号：US17147487

申请日：2021-01-13

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Richard Graham ,  Lion Levi ,  Daniel Marcovitch ,  Larry R. Dennison ,  Aviad Levy ,  Noam Bloch ,  Gil Bloch

IPC: H04L67/1097 ,  H04L67/60

CPC classification number: H04L67/1097 ,  H04L67/60

Abstract: An apparatus includes one or more ports for connecting to a communication network, processing circuitry and a message aggregation circuit (MAC). The processing circuitry is configured to communicate messages over the communication network via the one or more ports. The MAC is configured to receive messages, which originate in one or more source processes and are destined to one or more destination processes, to aggregate two or more of the messages that share a common destination into an aggregated message, and to send the aggregated message using the processing circuitry over the communication network.

公开(公告)号：US11425027B2

公开(公告)日：2022-08-23

申请号：US17086412

申请日：2020-11-01

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Michael Gandelman ,  Jose Yallouz ,  Lion Levi ,  Tamir Ronen ,  Aviad Levy ,  Vladimir Koushnir

IPC: H04L45/00 ,  H04L45/02 ,  H04L45/122 ,  H04L49/00

Abstract: An apparatus includes an interface and a processor. The interface communicates with a network including network elements interconnected in a Cartesian topology. The processor defines first and second groups of turns, each turn includes a hop from a previous network element to a current network element and a hop from the current network element to a next network element. Based on the turns, the processor specifies rules that when applied to packets traversing respective network elements, guarantee that no deadlock conditions occur in the network. The rules for a given network element include (i) forwarding rules to reach a given target without traversing the turns of the second group, and (ii) Virtual Lane (VL) modification rules for reassigning packets, which traverse turns of the first group and which are assigned to a first VL, to a different second VL. The processor configures the given network element with the rules.

公开(公告)号：US11782895B2

公开(公告)日：2023-10-10

申请号：US17013697

申请日：2020-09-07

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Aviad Levy ,  Gil Levy ,  Pedro Reviriego ,  Salvatore Pontarelli

IPC: G06F16/22 ,  G06F1/12

CPC classification number: G06F16/2255 ,  G06F1/12

Abstract: A hashing apparatus includes a memory and circuitry. The memory stores (i) multiple hash tables storing associative entries, each including at least one entry key and a respective value, the hash tables are associated with respective different hash functions, and an associative entry is accessible by applying the relevant hash function to a key matching an entry key in the associative entry, and (ii) an affinity table that stores table-selectors for selecting hash tables with which to start a key lookup. The circuitry receives a key, reads from the affinity table, by applying an affinity function to the key, a table-selector that selects a hash table, accesses in the selected hash table an associative entry by applying the hash function associated with the selected hash table to the key, and in response to detecting that the key matches an entry key in the associative entry, outputs the respective value.

公开(公告)号：US20220075766A1

公开(公告)日：2022-03-10

申请号：US17013697

申请日：2020-09-07

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Aviad Levy ,  Gil Levy ,  Pedro Reviriego ,  Salvatore Pontarelli

IPC: G06F16/22 ,  G06F1/12

Abstract: A hashing apparatus includes a memory and circuitry. The memory stores (i) multiple hash tables storing associative entries, each including at least one entry key and a respective value, the hash tables are associated with respective different hash functions, and an associative entry is accessible by applying the relevant hash function to a key matching an entry key in the associative entry, and (ii) an affinity table that stores table-selectors for selecting hash tables with which to start a key lookup. The circuitry receives a key, reads from the affinity table, by applying an affinity function to the key, a table-selector that selects a hash table, accesses in the selected hash table an associative entry by applying the hash function associated with the selected hash table to the key, and in response to detecting that the key matches an entry key in the associative entry, outputs the respective value.

公开(公告)号：US11411911B2

公开(公告)日：2022-08-09

申请号：US17079543

申请日：2020-10-26

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Lion Levi ,  Vladimir Koushnir ,  Matty Kadosh ,  Gil Bloch ,  Aviad Levy ,  Liran Liss ,  Dvir Libhaber

IPC: H04L61/103 ,  H04L45/02

Abstract: A router includes routing circuitry and a plurality of ports. The routing circuitry is configured to receive from a first subnetwork, via one of the ports, a packet destined to be delivered to a target node located in a second subnetwork, to select a mapping, from among two or more mappings, depending on a topological relation between the first subnetwork and the second subnetwork, to map a Layer-3 address of the packet into a Layer-2 address using the selected mapping, and to forward the packet via another one of the ports to the Layer-2 address.

公开(公告)号：US20220141125A1

公开(公告)日：2022-05-05

申请号：US17086412

申请日：2020-11-01

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Michael Gandelman ,  Jose Yallouz ,  Lion Levi ,  Tamir Ronen ,  Aviad Levy ,  Vladimir Koushnir

IPC: H04L12/733 ,  H04L12/751 ,  H04L12/721 ,  H04L12/707 ,  H04L12/935

Abstract: An apparatus includes an interface and a processor. The interface communicates with a network including network elements interconnected in a Cartesian topology. The processor defines first and second groups of turns, each turn includes a hop from a previous network element to a current network element and a hop from the current network element to a next network element. Based on the turns, the processor specifies rules that when applied to packets traversing respective network elements, guarantee that no deadlock conditions occur in the network. The rules for a given network element include (i) forwarding rules to reach a given target without traversing the turns of the second group, and (ii) Virtual Lane (VL) modification rules for reassigning packets, which traverse turns of the first group and which are assigned to a first VL, to a different second VL. The processor configures the given network element with the rules.