公开(公告)号：US20140136926A1

公开(公告)日：2014-05-15

申请号：US14156988

申请日：2014-01-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： William H. Radke ,  Shuba Swaminathan ,  Brady L. Keays

IPC: G06F11/10

CPC classification number: G06F11/10 ,  G06F11/1068

Abstract: Methods are described that facilitate the detection and correction of data in memory systems or devices by encoding the data bits of a memory row or block in a non-systematic ECC code. This allows memory embodiments of the present invention to utilize reduced complexity error detection and correction hardware and/or routines to efficiently detect and correct corrupted user data in a segment of memory, such as a sector, word line row, or erase block. User data is not stored in a plaintext format in the memory array, allowing for an increased level of data security. The ECC code is distributed throughout the stored data in the memory segment, increasing the robustness of the ECC code and its resistance to damage or data corruption.

Abstract translation: 描述了通过对非系统ECC代码中的存储器行或块的数据位进行编码来促进存储器系统或设备中的数据的检测和校正的方法。 这允许本发明的存储器实施例利用降低复杂性的错误检测和校正硬件和/或例程来有效地检测和校正存储器的段（例如扇区，字线行或擦除块）中的损坏的用户数据。 用户数据不以存储器阵列中的明文格式存储，从而可以提高数据安全级别。 ECC代码分布在存储器段中的所有存储的数据中，增加ECC代码的鲁棒性及其对损坏或数据损坏的抵抗力。

公开(公告)号：US20220066945A1

公开(公告)日：2022-03-03

申请号：US17458781

申请日：2021-08-27

Applicant: Micron Technology, Inc.

Inventor： Wanmo Wong ,  Brady L. Keays

IPC: G06F12/1009

Abstract: Methods, systems, and devices for techniques for managed NAND translation with embedded memory systems are described. A host system may generate a first command to access a logical memory address associated with a memory system. The host system may identify a physical memory address of the memory system based on generating the first command. The host system may output to the memory system a second command and the physical memory address, where the second command may be communicated to the memory device using a protocol associated with a controller of the memory system. The memory system may then access memory cells in a memory device associated with the physical memory address based on receiving the second command and the physical memory address.

公开(公告)号：US08954818B2

公开(公告)日：2015-02-10

申请号：US14173256

申请日：2014-02-05

Applicant: Micron Technology, Inc.

Inventor： William H. Radke ,  Shuba Swaminathan ,  Brady L. Keays

IPC: H03M13/00 ,  H03M13/09 ,  G06F11/10

CPC classification number: H03M13/096 ,  G06F11/1008

Abstract: An embodiment of a method of operating a memory device includes reading data from a memory array into a data buffer, checking the data using a first checker, checking the data using a second checker, and when an error is detected by the first checker and the error is not detected by the second checker returning the data to the memory array from the data buffer.

Abstract translation: 操作存储器件的方法的实施例包括将数据从存储器阵列读入数据缓冲器，使用第一校验器检查数据，使用第二校验器检查数据，以及当第一校验器检测到错误时， 第二个检查器从数据缓冲区将数据返回到存储器阵列时未检测到错误。

公开(公告)号：US08782493B2

公开(公告)日：2014-07-15

申请号：US13964682

申请日：2013-08-12

Applicant: Micron Technology, Inc.

Inventor： Brady L. Keays ,  Shuba Swaminathan ,  William H. Radke

IPC: G11C29/00

CPC classification number: G06F11/10 ,  G06F11/1048 ,  H03M13/132 ,  H03M13/1515

Abstract: Methods of correcting data in a memory, and memories adapted to correct data, include prioritizing error correction of the read data in response to locations and likely states of known bad or questionable data positions of a segment of a memory array selected for reading.

Abstract translation: 校正存储器中的数据以及适于校正数据的存储器的方法包括响应于选择用于读取的存储器阵列的段的已知不良或可疑数据位置的位置和可能状态来优先考虑读取数据的错误校正。

公开(公告)号：US20140189475A1

公开(公告)日：2014-07-03

申请号：US14173256

申请日：2014-02-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： William H. Radke ,  Shuba Swaminathan ,  Brady L. Keays

IPC: H03M13/09

CPC classification number: H03M13/096 ,  G06F11/1008

Abstract: An embodiment of a method of operating a memory device includes reading data from a memory array into a data buffer, checking the data using a first checker, checking the data using a second checker, and when an error is detected by the first checker and the error is not detected by the second checker returning the data to the memory array from the data buffer.

Abstract translation: 操作存储器件的方法的实施例包括将数据从存储器阵列读入数据缓冲器，使用第一校验器检查数据，使用第二校验器检查数据，以及当第一校验器检测到错误时， 第二个检查器从数据缓冲区将数据返回到存储器阵列时未检测到错误。

公开(公告)号：US20240361961A1

公开(公告)日：2024-10-31

申请号：US18660112

申请日：2024-05-09

Applicant: Micron Technology, Inc.

Inventor： Wanmo Wong ,  Brady L. Keays

IPC: G06F3/06

CPC classification number: G06F3/0688 ,  G06F3/061 ,  G06F3/0661

Abstract: Methods, systems, and devices for techniques for managed NAND translation with embedded memory systems are described. A host system may generate a first command to access a logical memory address associated with a memory system. The host system may identify a physical memory address of the memory system based on generating the first command. The host system may output to the memory system a second command and the physical memory address, where the second command may be communicated to the memory device using a protocol associated with a controller of the memory system. The memory system may then access memory cells in a memory device associated with the physical memory address based on receiving the second command and the physical memory address.

公开(公告)号：US12001727B2

公开(公告)日：2024-06-04

申请号：US17458781

申请日：2021-08-27

Applicant: Micron Technology, Inc.

Inventor： Wanmo Wong ,  Brady L. Keays

IPC: G06F3/06

CPC classification number: G06F3/0688 ,  G06F3/061 ,  G06F3/0661

Abstract: Methods, systems, and devices for techniques for managed NAND translation with embedded memory systems are described. A host system may generate a first command to access a logical memory address associated with a memory system. The host system may identify a physical memory address of the memory system based on generating the first command. The host system may output to the memory system a second command and the physical memory address, where the second command may be communicated to the memory device using a protocol associated with a controller of the memory system. The memory system may then access memory cells in a memory device associated with the physical memory address based on receiving the second command and the physical memory address.

公开(公告)号：US09229802B2

公开(公告)日：2016-01-05

申请号：US14156988

申请日：2014-01-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： William H. Radke ,  Shuba Swaminathan ,  Brady L. Keays

IPC: G06F11/10

CPC classification number: G06F11/10 ,  G06F11/1068

Abstract: Methods are described that facilitate the detection and correction of data in memory systems or devices by encoding the data bits of a memory row or block in a non-systematic ECC code. This allows memory embodiments of the present invention to utilize reduced complexity error detection and correction hardware and/or routines to efficiently detect and correct corrupted user data in a segment of memory, such as a sector, word line row, or erase block. User data is not stored in a plaintext format in the memory array, allowing for an increased level of data security. The ECC code is distributed throughout the stored data in the memory segment, increasing the robustness of the ECC code and its resistance to damage or data corruption.

Abstract translation: 描述了通过对非系统ECC代码中的存储器行或块的数据位进行编码来促进存储器系统或设备中的数据的检测和校正的方法。 这允许本发明的存储器实施例利用降低复杂性的错误检测和校正硬件和/或例程来有效地检测和校正存储器的段（例如扇区，字线行或擦除块）中的损坏的用户数据。 用户数据不以存储器阵列中的明文格式存储，从而可以提高数据安全级别。 ECC代码分布在存储器段中的所有存储的数据中，增加ECC代码的鲁棒性及其对损坏或数据损坏的抵抗力。

公开(公告)号：US08792277B2

公开(公告)日：2014-07-29

申请号：US14027381

申请日：2013-09-16

Applicant: Micron Technology, Inc.

Inventor： David Eggleston ,  Anthony Moschopoulos ,  Michael Murray ,  Brady L. Keays

IPC: G11C16/06

CPC classification number: G06F11/1008 ,  G06F11/1068 ,  G11C16/16

Abstract: Split data error correction code (ECC) circuits including a control circuit coupled to an error correction code (ECC) circuit. The ECC circuit is adapted to generate at least one ECC code from user data of a first physical sector during a data access. The split data ECC circuit is adapted to write the at least one ECC code to a second physical sector if the data access is a write access and to compare the at least one generated ECC code with at least one ECC code stored in a second physical sector if the data access is a read access.

Abstract translation: 分割数据纠错码（ECC）电路，包括耦合到纠错码（ECC）电路的控制电路。 ECC电路适于在数据访问期间从第一物理扇区的用户数据生成至少一个ECC码。 如果数据访问是写访问，则分割数据ECC电路适于将至少一个ECC代码写入第二物理扇区，并且将至少一个生成的ECC代码与存储在第二物理扇区中的至少一个ECC代码进行比较 如果数据访问是读访问。

公开(公告)号：US20130332798A1

公开(公告)日：2013-12-12

申请号：US13964682

申请日：2013-08-12

Applicant: Micron Technology, Inc.

Inventor： Brady L. Keays ,  Shuba Swaminathan ,  William H. Radke

IPC: G06F11/10

CPC classification number: G06F11/10 ,  G06F11/1048 ,  H03M13/132 ,  H03M13/1515

Abstract: Methods of correcting data in a memory, and memories adapted to correct data, include prioritizing error correction of the read data in response to locations and likely states of known bad or questionable data positions of a segment of a memory array selected for reading.

Abstract translation: 校正存储器中的数据以及适于校正数据的存储器的方法包括响应于选择用于读取的存储器阵列的段的已知不良或可疑数据位置的位置和可能状态来优先考虑读取数据的错误校正。