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    FREQUENCY SYNTHESIS FOR MEMORY INPUT-OUTPUT OPERATIONS
    2.
    发明申请
    FREQUENCY SYNTHESIS FOR MEMORY INPUT-OUTPUT OPERATIONS 有权
    用于存储器输入输出操作的频率合成

    公开(公告)号：US20160329090A1

    公开(公告)日：2016-11-10

    申请号：US14707878

    申请日：2015-05-08

    Applicant: Micron Technology, Inc.

    Inventor： Dean Gans ,  Moo Sung Chae ,  Daniel Skinner

    IPC: G11C11/4076 ,  G11C11/4096

    CPC classification number: G11C11/4076 ,  G11C7/062 ,  G11C7/1006 ,  G11C7/14 ,  G11C7/222 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/2254

    Abstract: A memory channel including an internal clock circuit is disclosed. The clock circuit may synthesize an internal clock signal for use by one or more components of the memory channel. The internal clock signal may have a different frequency than an external clock frequency. The memory channel may include multiple clock circuits that generate multiple internal clock signals. Each portion of the memory channel associated with a different clock circuit may be phase and/or frequency independent of the other portions of the memory channel. The clock circuit may synthesize an internal clock signal based on an external clock signal. The clock circuit may use encoded timing data from an encoded I/O scheme to align the phase of the internal clock signal to a data signal.

    Abstract translation: 公开了一种包括内部时钟电路的存储通道。 时钟电路可以合成内部时钟信号以供存储器通道的一个或多个组件使用。 内部时钟信号可能具有与外部时钟频率不同的频率。 存储器通道可以包括产生多个内部时钟信号的多个时钟电路。 与不同时钟电路相关联的存储器通道的每个部分可以是与存储器通道的其它部分无关的相位和/或频率。 时钟电路可以基于外部时钟信号合成内部时钟信号。 时钟电路可以使用来自编码I / O方案的编码定时数据将内部时钟信号的相位对准数据信号。

    Frequency synthesis for memory input-output operations
    3.
    发明授权
    Frequency synthesis for memory input-output operations 有权

    公开(公告)号：US10796746B2

    公开(公告)日：2020-10-06

    申请号：US16138621

    申请日：2018-09-21

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Dean Gans ,  Moo Sung Chae ,  Daniel Skinner

    IPC: G11C11/4076 ,  G11C11/4096 ,  G11C7/22 ,  G11C11/4093 ,  G11C7/10 ,  G11C7/14 ,  G11C7/06

    Abstract: A memory channel including an internal clock circuit is disclosed. The clock circuit may synthesize an internal clock signal for use by one or more components of the memory channel. The internal clock signal may have a different frequency than an external clock frequency. The memory channel may include multiple clock circuits that generate multiple internal clock signals. Each portion of the memory channel associated with a different clock circuit may be phase and/or frequency independent of the other portions of the memory channel. The clock circuit may synthesize an internal clock signal based on an external clock signal. The clock circuit may use encoded timing data from an encoded I/O scheme to align the phase of the internal clock signal to a data signal.

    Frequency synthesis for memory input-output operations
    4.
    发明授权
    Frequency synthesis for memory input-output operations 有权

    公开(公告)号：US10115449B2

    公开(公告)日：2018-10-30

    申请号：US15415655

    申请日：2017-01-25

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Dean Gans ,  Moo Sung Chae ,  Daniel Skinner

    IPC: G11C7/00 ,  G11C11/4076 ,  G11C11/4096 ,  G11C11/4093

    Abstract: A memory channel including an internal clock circuit is disclosed. The clock circuit may synthesize an internal clock signal for use by one or more components of the memory channel. The internal clock signal may have a different frequency than an external clock frequency. The memory channel may include multiple clock circuits that generate multiple internal clock signals. Each portion of the memory channel associated with a different clock circuit may be phase and/or frequency independent of the other portions of the memory channel. The clock circuit may synthesize an internal clock signal based on an external clock signal. The clock circuit may use encoded timing data from an encoded I/O scheme to align the phase of the internal clock signal to a data signal.

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