公开(公告)号：US11270754B2

公开(公告)日：2022-03-08

申请号：US16723386

申请日：2019-12-20

Applicant: Micron Technology, Inc.

Inventor： Dean Gans

IPC: G11C5/14 ,  G11C11/4074 ,  G11C11/4076

Abstract: According to one embodiment, an apparatus is disclosed. The apparatus includes a first power supply having a first fixed voltage, a second power supply having a second fixed voltage, a plurality of circuits coupled to the first power supply via a first switch and the second power supply via a second switch, and a power control circuit configured to selectively enable one of the first switch and the second switch responsive to power demand information.

公开(公告)号：US11017879B1

公开(公告)日：2021-05-25

申请号：US16723532

申请日：2019-12-20

Applicant: Micron Technology, Inc.

Inventor： James S. Rehmeyer ,  Christopher G. Wieduwilt ,  George Raad ,  Seth Eichmeyer ,  Dean Gans

IPC: G11C17/16 ,  G11C29/02 ,  G11C29/18 ,  G11C29/00

Abstract: Methods, systems, and devices for adjustable column address scramble using fuses are described. A testing device may detect a first error in a first column plane of a memory array and a second error in a second column plane of the memory array. The testing device may identify a first column address of the first column plane associated with the first error and a second column address of the second column plane based on detecting the first error and the second error. The testing device may determine, for the first column plane, a configuration for scrambling column addresses of the first column plane to different column addresses of the first column plane. In some cases, the testing device may perform a fuse blow of a fuse associated with the first column plane to implement the determined configuration.

公开(公告)号：US10467158B2

公开(公告)日：2019-11-05

申请号：US16035452

申请日：2018-07-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kang-Yong Kim ,  Dean Gans

IPC: G11C7/22 ,  G06F13/16 ,  G06F9/30

Abstract: Apparatuses and methods including memory commands for semiconductor memories are described. A controller provides a memory system with memory commands to access memory. The commands are decoded to provide internal signals and commands for performing operations, such as operations to access the memory array. The memory commands provided for accessing memory may include timing command and access commands. Examples of access commands include a read command and a write command. Timing commands may be used to control the timing of various operations, for example, for a corresponding access command. The timing commands may include opcodes that set various modes of operation during an associated access operation for an access command.

公开(公告)号：US20190334505A1

公开(公告)日：2019-10-31

申请号：US16505369

申请日：2019-07-08

Applicant: Micron Technology, Inc.

Inventor： Dean Gans

IPC: H03H11/28 ,  H03H11/54 ,  G11C29/02 ,  G11C7/10 ,  H03K19/00

Abstract: Apparatuses and methods for calibrating adjustable impedances of a semiconductor device are disclosed in the present application. An example apparatus includes a register configured to store impedance calibration information and further includes programmable termination resistances having a programmable impedance. The example apparatus further includes an impedance calibration circuit configured to perform a calibration operation to determine calibration parameters for setting the programmable impedance of the programmable termination resistances. The impedance calibration circuit is further configured to program the impedance calibration information in the register related to the calibration operation.

公开(公告)号：US20190163653A1

公开(公告)日：2019-05-30

申请号：US16035452

申请日：2018-07-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kang-Yong Kim ,  Dean Gans

IPC: G06F13/16 ,  G06F9/30

CPC classification number: G06F13/1689 ,  G06F9/30145 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028

Abstract: Apparatuses and methods including memory commands for semiconductor memories are described. A controller provides a memory system with memory commands to access memory. The commands are decoded to provide internal signals and commands for performing operations, such as operations to access the memory array. The memory commands provided for accessing memory may include timing command and access commands. Examples of access commands include a read command and a write command. Timing commands may be used to control the timing of various operations, for example, for a corresponding access command. The timing commands may include opcodes that set various modes of operation during an associated access operation for an access command.

公开(公告)号：US20190163652A1

公开(公告)日：2019-05-30

申请号：US16035414

申请日：2018-07-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kang-Yong Kim ,  Dean Gans

IPC: G06F13/16 ,  G06F9/30

Abstract: Apparatuses and methods including memory commands for semiconductor memories are described. A controller provides a memory system with memory commands to access memory. The commands are decoded to provide internal signals and commands for performing operations, such as operations to access the memory array. The memory commands provided for accessing memory may include timing command and access commands. Examples of access commands include a read command and a write command. Timing commands may be used to control the timing of various operations, for example, for a corresponding access command. The timing commands may include opcodes that set various modes of operation during an associated access operation for an access command.

公开(公告)号：US20190027208A1

公开(公告)日：2019-01-24

申请号：US16138621

申请日：2018-09-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dean Gans ,  Moo Sung Chae ,  Daniel Skinner

IPC: G11C11/4076 ,  G11C7/22 ,  G11C11/4093 ,  G11C11/4096 ,  G11C7/06 ,  G11C7/10 ,  G11C7/14

CPC classification number: G11C11/4076 ,  G11C7/062 ,  G11C7/1006 ,  G11C7/14 ,  G11C7/222 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/2254

Abstract: A memory channel including an internal clock circuit is disclosed. The clock circuit may synthesize an internal clock signal for use by one or more components of the memory channel. The internal clock signal may have a different frequency than an external clock frequency. The memory channel may include multiple clock circuits that generate multiple internal clock signals. Each portion of the memory channel associated with a different clock circuit may be phase and/or frequency independent of the other portions of the memory channel. The clock circuit may synthesize an internal clock signal based on an external clock signal. The clock circuit may use encoded timing data from an encoded I/O scheme to align the phase of the internal clock signal to a data signal.

公开(公告)号：US20180278461A1

公开(公告)日：2018-09-27

申请号：US15465421

申请日：2017-03-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： TIMOTHY M. HOLLIS ,  Dean Gans ,  Randon Richards ,  Bruce W. Schober

IPC: H04L12/24 ,  H04L12/863 ,  H04L25/03

CPC classification number: H04L41/0226 ,  H04L47/6225

Abstract: According to one embodiment, A data buffer is described. The data buffer comprises a first input/output circuit configured to receive and provide a first signal encoded according to a first communications protocol, a second input/output circuit configured to receive and provide a second signal encoded according to a second communications protocol, and a conversion circuit coupled to the first and second input/output circuits and configured to convert the first signal to the second signal and to convert the second signal to the first signal.

公开(公告)号：US20180246822A1

公开(公告)日：2018-08-30

申请号：US15963615

申请日：2018-04-26

Applicant: Micron Technology, Inc.

Inventor： Dean Gans ,  Bruce Schober ,  Moo Sung Chae

IPC: G06F13/16 ,  G06F13/40

CPC classification number: G06F13/1689 ,  G06F13/4068

Abstract: Apparatuses and methods for asymmetric input/output interfaces for memory are disclosed. An example apparatus may include a receiver and a transmitter. The receiver may be configured to receive first data signals having a first voltage swing and having a first slew rate. The transmitter may be configured to provide second data signals having a second voltage swing and having a second slew rate, wherein the first and second voltage swings are different, and wherein the first and second slew rates are different.

公开(公告)号：US12197355B2

公开(公告)日：2025-01-14

申请号：US17751298

申请日：2022-05-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kang-Yong Kim ,  Dean Gans

IPC: G06F13/16 ,  G06F9/30 ,  G11C7/22 ,  G11C29/02

Abstract: Apparatuses and methods including memory commands for semiconductor memories are described. A controller provides a memory system with memory commands to access memory. The commands are decoded to provide internal signals and commands for performing operations, such as operations to access the memory array. The memory commands provided for accessing memory may include timing command and access commands. Examples of access commands include a read command and a write command. Timing commands may be used to control the timing of various operations, for example, for a corresponding access command. The timing commands may include opcodes that set various modes of operation during an associated access operation for an access command.