公开(公告)号：US20140347948A1

公开(公告)日：2014-11-27

申请号：US14455456

申请日：2014-08-08

Applicant: Micron Technology, Inc.

Inventor： Anthony D. Veches ,  Joshua E. Alzheimer ,  Dennis R. Blankenship

IPC: G11C8/12

CPC classification number: G11C8/12 ,  G11C5/02 ,  G11C5/14 ,  G11C7/00 ,  G11C7/10

Abstract: Apparatuses and methods including a plurality of memory units are disclosed. An example apparatus includes a plurality of memory units. Each of the plurality of memory units include a master/slave identification (ID) node coupled to a first voltage source node via a resistive element. Each of the plurality of memory units further include a master/slave ID circuit configured to determine whether a memory unit is a master memory unit or a slave memory unit based on a voltage level detected at the master/slave ID node. The master/slave ID node of each of the plurality of memory units other than a first memory unit is further coupled to a respective second voltage source node via a through—substrate via (TSV) of a respective adjacent memory unit of the plurality of memory units.

Abstract translation: 公开了包括多个存储单元的装置和方法。 示例性装置包括多个存储单元。 多个存储单元中的每一个包括经由电阻元件耦合到第一电压源节点的主/从标识（ID）节点。 多个存储单元中的每一个还包括主/从ID电路，其被配置为基于在主/从ID节点处检测到的电压电平来确定存储器单元是主存储器单元还是从存储器单元。 除了第一存储器单元之外的多个存储器单元中的每一个的主/从ID节点还经由穿过基板经由多个存储器中的相应相邻存储器单元的（TSV）耦合到相应的第二电压源节点 单位。

公开(公告)号：US08817547B2

公开(公告)日：2014-08-26

申请号：US13709792

申请日：2012-12-10

Applicant: Micron Technology, Inc.

Inventor： Anthony D. Veches ,  Joshua E. Alzheimer ,  Dennis R. Blankenship

IPC: G11C7/10

CPC classification number: G11C8/12 ,  G11C5/02 ,  G11C5/14 ,  G11C7/00 ,  G11C7/10

Abstract: Apparatuses and methods including a plurality of memory units are disclosed. An example apparatus includes a plurality of memory units. Each of the plurality of memory units include a master/slave identification (ID) node coupled to a first voltage source node via a resistive element. Each of the plurality of memory units further include a master/slave ID circuit configured to determine whether a memory unit is a master memory unit or a slave memory unit based on a voltage level detected at the master/slave ID node. The master/slave ID node of each of the plurality of memory units other than a first memory unit is further coupled to a respective second voltage source node via a through-substrate via (TSV) of a respective adjacent memory unit of the plurality of memory units.

Abstract translation: 公开了包括多个存储单元的装置和方法。 示例性装置包括多个存储单元。 多个存储单元中的每一个包括经由电阻元件耦合到第一电压源节点的主/从标识（ID）节点。 多个存储单元中的每一个还包括主/从ID电路，其被配置为基于在主/从ID节点处检测到的电压电平来确定存储器单元是主存储器单元还是从存储器单元。 除了第一存储器单元之外的多个存储器单元中的每一个的主/从ID节点还经由穿过基板经由多个存储器中的相应相邻存储器单元的（TSV）耦合到相应的第二电压源节点 单位。

公开(公告)号：US09305625B2

公开(公告)日：2016-04-05

申请号：US14455456

申请日：2014-08-08

Applicant: Micron Technology, Inc.

Inventor： Anthony D. Veches ,  Joshua E. Alzheimer ,  Dennis R. Blankenship

IPC: G11C7/00 ,  G11C8/12 ,  G11C5/14 ,  G11C5/02 ,  G11C7/10

CPC classification number: G11C8/12 ,  G11C5/02 ,  G11C5/14 ,  G11C7/00 ,  G11C7/10

Abstract: Apparatuses and methods including a plurality of memory units are disclosed. An example apparatus includes a plurality of memory units. Each of the plurality of memory units include a master/slave identification (ID) node coupled to a first voltage source node via a resistive element. Each of the plurality of memory units further include a master/slave ID circuit configured to determine whether a memory unit is a master memory unit or a slave memory unit based on a voltage level detected at the master/slave ID node. The master/slave ID node of each of the plurality of memory units other than a first memory unit is further coupled to a respective second voltage source node via a through—substrate via (TSV) of a respective adjacent memory unit of the plurality of memory units.

Abstract translation: 公开了包括多个存储单元的装置和方法。 示例性装置包括多个存储单元。 多个存储单元中的每一个包括经由电阻元件耦合到第一电压源节点的主/从标识（ID）节点。 多个存储单元中的每一个还包括主/从ID电路，其被配置为基于在主/从ID节点处检测到的电压电平来确定存储器单元是主存储器单元还是从存储器单元。 除了第一存储器单元之外的多个存储器单元中的每一个的主/从ID节点还经由穿过基板经由多个存储器中的相应相邻存储器单元的（TSV）耦合到相应的第二电压源节点 单位。

公开(公告)号：US20140160867A1

公开(公告)日：2014-06-12

申请号：US13709792

申请日：2012-12-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Anthony D. Veches ,  Joshua E. Alzheimer ,  Dennis R. Blankenship

IPC: G11C7/00

CPC classification number: G11C8/12 ,  G11C5/02 ,  G11C5/14 ,  G11C7/00 ,  G11C7/10

Abstract: Apparatuses and methods including a plurality of memory units are disclosed. An example apparatus includes a plurality of memory units. Each of the plurality of memory units include a master/slave identification (ID) node coupled to a first voltage source node via a resistive element. Each of the plurality of memory units further include a master/slave ID circuit configured to determine whether a memory unit is a master memory unit or a slave memory unit based on a voltage level detected at the master/slave ID node. The master/slave ID node of each of the plurality of memory units other than a first memory unit is further coupled to a respective second voltage source node via a through-substrate via (TSV) of a respective adjacent memory unit of the plurality of memory units.

Abstract translation: 公开了包括多个存储单元的装置和方法。 示例性装置包括多个存储单元。 多个存储单元中的每一个包括经由电阻元件耦合到第一电压源节点的主/从标识（ID）节点。 多个存储单元中的每一个还包括主/从ID电路，其被配置为基于在主/从ID节点处检测到的电压电平来确定存储器单元是主存储器单元还是从存储器单元。 除了第一存储器单元之外的多个存储器单元中的每一个的主/从ID节点还经由穿过基板经由多个存储器中的相应相邻存储器单元的（TSV）耦合到相应的第二电压源节点 单位。