公开(公告)号：US20240004754A1

公开(公告)日：2024-01-04

申请号：US18313656

申请日：2023-05-08

Applicant: Micron Technology, Inc.

Inventor： Anthony D. Veches

IPC: G06F11/10

CPC classification number: G06F11/1044 ,  G06F11/1072 ,  G06F11/1056 ,  G06F11/1052

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a memory device may select an option for a host device to access a memory array including a first portion configured to store user data and a second portion configured to store different data based on whether an ECC function of the memory device is enabled or disabled—e.g., storing ECC data when the ECC function is enabled, storing additional user data, metadata, or both when the ECC function is disabled. The host device may disable the ECC function and transmit an input to the memory device as to how to access the memory array. The memory device, based on the input, may select the option for the host device to access the memory array and communicate with the host device in accordance with the selected option.

公开(公告)号：US20230389207A1

公开(公告)日：2023-11-30

申请号：US17804789

申请日：2022-05-31

Applicant: Micron Technology, Inc.

Inventor： Anthony D. Veches

IPC: H05K5/02 ,  H01R12/70 ,  H05K7/20

CPC classification number: H05K5/026 ,  H01R12/7076 ,  H05K5/0286 ,  H05K7/20763

Abstract: This disclosure relates generally to interfaces between memory modules and circuit boards. More specifically, this disclosure relates to interfaces for coupling a memory module to a circuit board such that the memory module is arranged in a plane that is substantially parallel with a plane of the circuit board. Various embodiments disclosed herein include interfaces, memory modules including interfaces or portions of interfaces, and/or circuit boards including interfaces and/or portions of interfaces. Associated devices and systems are also disclosed.

公开(公告)号：US11721385B2

公开(公告)日：2023-08-08

申请号：US17400886

申请日：2021-08-12

Applicant: Micron Technology, Inc.

Inventor： Anthony D. Veches ,  Brian P. Callaway

IPC: G11C11/40 ,  G11C11/4074 ,  H01L25/065 ,  H01L23/00

CPC classification number: G11C11/4074 ,  H01L24/08 ,  H01L25/0657 ,  H01L2224/08145 ,  H01L2924/1436

Abstract: Methods, systems, and devices for dynamic power distribution for stacked memory are described. A stacked memory device may include switching components that support dynamic coupling between a shared power source of the memory device and circuitry associated with operating memory arrays of respective memory dies. In some examples, such techniques include coupling a power source with array circuitry based on an access activity or a degree of access activity for the array circuitry. In some examples, such techniques include isolating a power source from array circuitry based on a lack of access activity or a degree of access activity for the array circuitry. The dynamic coupling or isolation may be supported by various signaling of the memory device, such as signaling between memory dies, signaling between a memory die and a central controller, or signaling between the memory device and a host device.

公开(公告)号：US20230065314A1

公开(公告)日：2023-03-02

申请号：US17875802

申请日：2022-07-28

Applicant: Micron Technology, Inc.

Inventor： Anthony D. Veches

IPC: H01L27/16 ,  H01L23/38 ,  H01L35/32 ,  H01L35/34

Abstract: A memory device comprises multiple memory dice arranged vertically in a stack of memory dice and at least one thermoelectric die contacting the bulk silicon layer of at least one of the memory dice of the multiple memory dice. Each memory die of the multiple memory dice includes an active circuitry layer that includes memory cells of a memory array and a bulk silicon layer. The thermoelectric die is configured to one or both of reduce heat from the memory die when a current is applied to terminals of the thermoelectric die and generate a voltage at the terminals of the thermoelectric die when heat from the memory die is applied to the thermoelectric die.

公开(公告)号：US11586958B2

公开(公告)日：2023-02-21

申请号：US16840916

申请日：2020-04-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Di Wu ,  Anthony D. Veches ,  James S. Rehmeyer ,  Debra M. Bell ,  Libo Wang

IPC: G06N5/04 ,  G06N5/047 ,  G06K9/62 ,  G06N20/00

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, methods for performing operations associated with machine learning. Machine learning operations may include processing a data set, training a machine learning algorithm, and applying a trained algorithm to a data set. Some of the machine learning operations, such as pattern matching operations, may be performed within a memory device.

公开(公告)号：US20220319569A1

公开(公告)日：2022-10-06

申请号：US17221498

申请日：2021-04-02

Applicant: Micron Technology, Inc.

Inventor： Anthony D. Veches ,  Brian P. Callaway

IPC: G11C11/4074 ,  G06F13/16 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/525 ,  G11C11/22

Abstract: Methods, systems, and devices for power distribution for stacked memory are described. A memory die may be configured with one or more conductive paths for providing power to another memory die, where each conductive path may pass through the memory die but may be electrically isolated from circuitry for operating the memory die. Each conductive path may provide an electronic coupling between at least one of a first set of contacts of the memory die (e.g., couplable with a power source) and at least one of a second set of contacts of the memory die (e.g., couplable with another memory die). To support operations of the memory die, a contact of the first set may be coupled with circuitry for operating a memory array of the memory die, and to support operations of another memory die, another contact of the first set may be electrically isolated from the circuitry.

公开(公告)号：US20220122943A1

公开(公告)日：2022-04-21

申请号：US17565377

申请日：2021-12-29

Applicant: Micron Technology, Inc.

Inventor： Anthony D. Veches

IPC: H01L25/065 ,  H01L23/64 ,  H01L25/00

Abstract: Semiconductor die assemblies including stacked semiconductor dies having parallel plate capacitors formed between adjacent pairs of semiconductor dies in the stack, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die and a second semiconductor die stacked over the first semiconductor die. The first semiconductor die includes an upper surface having a first capacitor plate formed thereon, and the second semiconductor die includes a lower surface facing the upper surface of the first semiconductor die and having a second capacitor plate formed thereon. A dielectric material is formed at least partially between the first and second capacitor plates. The first capacitor plate, second capacitor plate, and dielectric material together form a capacitor that stores charge locally within the stack, and that can be accessed by the first and/or second semiconductor dies.

公开(公告)号：US11276454B2

公开(公告)日：2022-03-15

申请号：US16939669

申请日：2020-07-27

Applicant: Micron Technology, Inc.

Inventor： Dale H. Hiscock ,  Debra M. Bell ,  Michael Kaminski ,  Joshua E. Alzheimer ,  Anthony D. Veches ,  James S. Rehmeyer

IPC: G11C16/34 ,  G11C11/406 ,  G11C11/4074 ,  G11C16/10 ,  G11C11/4072

Abstract: Memory devices and systems with partial array refresh control over memory regions in a memory array, and associated methods, are disclosed herein. In one embodiment, a memory device includes a memory array having a first memory region and a second memory region. The memory device is configured to write data to the memory array in accordance with a programming sequence by initially writing data to unutilized memory cells of the first memory region before initially writing data to unutilized memory cells of the second memory region. The memory device is further configured to determine that the data stored on the first and/or second memory regions is not consolidated, and to consolidate at least a portion of the data by rewriting the portion of the data to physically or logically contiguous memory cells of the first memory region and/or the second memory region.

公开(公告)号：US20210064271A1

公开(公告)日：2021-03-04

申请号：US16553859

申请日：2019-08-28

Applicant: Micron Technology, Inc.

Inventor： Anthony D. Veches ,  Debra M. Bell ,  James S. Rehmeyer ,  Robert Bunnell ,  Nathaniel J. Meier

IPC: G06F3/06 ,  G11C17/16 ,  G11C17/18 ,  G11C11/4091 ,  G11C11/4072

Abstract: Memory devices and systems with automatic background precondition upon powerup, and associated methods, are disclosed herein. In one embodiment, a memory device includes a memory array having a plurality of memory cells at intersections of memory rows and memory columns. The memory device further includes sense amplifiers corresponding to the memory rows. When the memory device powers on, the memory device writes one or more memory cells of the plurality of memory cells to a random data state before executing an access command received from a user, a memory controller, or a host device of the memory device. In some embodiments, to write the one or more memory cells, the memory device fires multiple memory rows at the same time without powering corresponding sense amplifiers such that data stored on memory cells of the multiple memory rows is overwritten and corrupted.

公开(公告)号：US20200211626A1

公开(公告)日：2020-07-02

申请号：US16237115

申请日：2018-12-31

Applicant: Micron Technology, Inc.

Inventor： Dale H. Hiscock ,  Debra M. Bell ,  Michael Kaminski ,  Joshua E. Alzheimer ,  Anthony D. Veches ,  James S. Rehmeyer

IPC: G11C11/4093 ,  G11C11/406 ,  G11C11/4096 ,  G11C5/02 ,  H01L25/10 ,  G11C7/18

Abstract: Memory devices and systems with on-die data transfer capability, and associated methods, are disclosed herein. In one embodiment, a memory device includes an array of memory cells and a plurality of input/output lines operably connecting the array to data pads of the device. In some embodiments, the memory device can further include a global cache and/or a local cache. The memory device can be configured to internally transfer data stored at a first location in the array to a second location in the array without outputting the data from the memory device. To transfer the data, the memory device can copy data on one row of memory cells to another row of memory cells, directly write data to the second location from the first location using data read/write lines of the input/output lines, and/or read the data into and out of the global cache and/or the local cache.