公开(公告)号：US20230214130A1

公开(公告)日：2023-07-06

申请号：US17959131

申请日：2022-10-03

Applicant: Micron Technology, Inc.

Inventor： Joshua E. Alzheimer ,  Mow Yiak Goh ,  Loren J. Wooley

IPC: G06F3/06 ,  G06F11/10

CPC classification number: G06F3/0619 ,  G06F3/0673 ,  G06F3/0629 ,  G06F11/1044

Abstract: Memory with address-selectable data poisoning circuitry is disclosed herein. In one embodiment, a memory device comprises circuitry operably connected to a memory array. The circuitry can include memory row address registers and/or memory column address registers. Standard access commands or mode register write commands can be used to load a memory row address or a memory column address into the memory row address registers or the memory column address registers, respectively. During a read operation directed to a second memory row and/or column of the memory array, the circuitry can compare the second memory row to the first memory row and/or the second memory column to the first memory column, and can poison a data bit read from the memory array before the data bit is output from the memory device when the first and second memory row addresses match and/or when the first and second memory column addresses match.

公开(公告)号：US11276454B2

公开(公告)日：2022-03-15

申请号：US16939669

申请日：2020-07-27

Applicant: Micron Technology, Inc.

Inventor： Dale H. Hiscock ,  Debra M. Bell ,  Michael Kaminski ,  Joshua E. Alzheimer ,  Anthony D. Veches ,  James S. Rehmeyer

IPC: G11C16/34 ,  G11C11/406 ,  G11C11/4074 ,  G11C16/10 ,  G11C11/4072

Abstract: Memory devices and systems with partial array refresh control over memory regions in a memory array, and associated methods, are disclosed herein. In one embodiment, a memory device includes a memory array having a first memory region and a second memory region. The memory device is configured to write data to the memory array in accordance with a programming sequence by initially writing data to unutilized memory cells of the first memory region before initially writing data to unutilized memory cells of the second memory region. The memory device is further configured to determine that the data stored on the first and/or second memory regions is not consolidated, and to consolidate at least a portion of the data by rewriting the portion of the data to physically or logically contiguous memory cells of the first memory region and/or the second memory region.

公开(公告)号：US20210311822A1

公开(公告)日：2021-10-07

申请号：US17350099

申请日：2021-06-17

Applicant: Micron Technology, Inc.

Inventor： Aaron Jannusch ,  Brett K. Dodds ,  Debra M. Bell ,  Joshua E. Alzheimer ,  Scott E. Smith

IPC: G06F11/10

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a host device may access a group of memory cells (e.g., portion of an array configurable to store ECC parity bits) otherwise reserved for ECC functionality of a memory device. The memory device may include a register to indicate whether its ECC functionality is enabled or disabled. When the register indicates the ECC functionality is disabled, the memory device may increase a storage capacity available to the host device by making the group of memory cells available for user-accessible data. Additionally or alternatively, the memory device may store metadata associated with various operational aspects of the memory device in the group of memory cells. Moreover, the memory device may modify a burst length to accommodate additional information to be stored in or read from the group of memory cells.

公开(公告)号：US20210241821A1

公开(公告)日：2021-08-05

申请号：US17234725

申请日：2021-04-19

Applicant: Micron Technology, Inc.

Inventor： Dale H. Hiscock ,  Michael Kaminski ,  Joshua E. Alzheimer ,  John H. Gentry

IPC: G11C11/406 ,  G11C11/4096 ,  G11C11/4074

Abstract: Memory devices and systems with configurable die refresh stagger, and associated methods, are disclosed herein. In one embodiment, a memory system includes two or more memory dies. At least one memory die includes a fuse array storing refresh information that specifies a refresh group of the memory die. In these and other embodiments, at least one memory die includes a refresh group terminal and refresh group detect circuitry electrically connected to the refresh group terminal. The at least one memory die is configured to detect a refresh group of the memory die and to delay its refresh operation by a time delay corresponding to the refresh group. In this manner, refresh operations of the two or more memory dies can be staggered to reduce peak current demand of the memory system.

公开(公告)号：US10991413B2

公开(公告)日：2021-04-27

申请号：US16502680

申请日：2019-07-03

Applicant: Micron Technology, Inc.

Inventor： Dale H. Hiscock ,  Michael Kaminski ,  Joshua E. Alzheimer ,  John H. Gentry

IPC: G11C11/406 ,  G11C11/4074 ,  G11C11/4096

Abstract: Memory devices and systems with configurable die refresh stagger, and associated methods, are disclosed herein. In one embodiment, a memory system includes two or more memory dies. At least one memory die includes a fuse array storing refresh information that specifies a refresh group of the memory die. In these and other embodiments, at least one memory die includes a refresh group terminal and refresh group detect circuitry electrically connected to the refresh group terminal. The at least one memory die is configured to detect a refresh group of the memory die and to delay its refresh operation by a time delay corresponding to the refresh group. In this manner, refresh operations of the two or more memory dies can be staggered to reduce peak current demand of the memory system.

公开(公告)号：US20200211626A1

公开(公告)日：2020-07-02

申请号：US16237115

申请日：2018-12-31

Applicant: Micron Technology, Inc.

Inventor： Dale H. Hiscock ,  Debra M. Bell ,  Michael Kaminski ,  Joshua E. Alzheimer ,  Anthony D. Veches ,  James S. Rehmeyer

IPC: G11C11/4093 ,  G11C11/406 ,  G11C11/4096 ,  G11C5/02 ,  H01L25/10 ,  G11C7/18

Abstract: Memory devices and systems with on-die data transfer capability, and associated methods, are disclosed herein. In one embodiment, a memory device includes an array of memory cells and a plurality of input/output lines operably connecting the array to data pads of the device. In some embodiments, the memory device can further include a global cache and/or a local cache. The memory device can be configured to internally transfer data stored at a first location in the array to a second location in the array without outputting the data from the memory device. To transfer the data, the memory device can copy data on one row of memory cells to another row of memory cells, directly write data to the second location from the first location using data read/write lines of the input/output lines, and/or read the data into and out of the global cache and/or the local cache.

公开(公告)号：US20140160867A1

公开(公告)日：2014-06-12

申请号：US13709792

申请日：2012-12-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Anthony D. Veches ,  Joshua E. Alzheimer ,  Dennis R. Blankenship

IPC: G11C7/00

CPC classification number: G11C8/12 ,  G11C5/02 ,  G11C5/14 ,  G11C7/00 ,  G11C7/10

Abstract: Apparatuses and methods including a plurality of memory units are disclosed. An example apparatus includes a plurality of memory units. Each of the plurality of memory units include a master/slave identification (ID) node coupled to a first voltage source node via a resistive element. Each of the plurality of memory units further include a master/slave ID circuit configured to determine whether a memory unit is a master memory unit or a slave memory unit based on a voltage level detected at the master/slave ID node. The master/slave ID node of each of the plurality of memory units other than a first memory unit is further coupled to a respective second voltage source node via a through-substrate via (TSV) of a respective adjacent memory unit of the plurality of memory units.

Abstract translation: 公开了包括多个存储单元的装置和方法。 示例性装置包括多个存储单元。 多个存储单元中的每一个包括经由电阻元件耦合到第一电压源节点的主/从标识（ID）节点。 多个存储单元中的每一个还包括主/从ID电路，其被配置为基于在主/从ID节点处检测到的电压电平来确定存储器单元是主存储器单元还是从存储器单元。 除了第一存储器单元之外的多个存储器单元中的每一个的主/从ID节点还经由穿过基板经由多个存储器中的相应相邻存储器单元的（TSV）耦合到相应的第二电压源节点 单位。

公开(公告)号：US12198774B2

公开(公告)日：2025-01-14

申请号：US17710601

申请日：2022-03-31

Applicant: Micron Technology, Inc.

Inventor： Joshua E. Alzheimer

IPC: G11C29/36 ,  G11C7/10 ,  G11C29/12

Abstract: A memory device may include sideband circuitry to provide additional functionality without interfering with normal operations of the memory device. The memory device may also include sideband pins to provide sideband information to an external device. The sideband information may include various digital or analog signals. In some cases, a sideband circuit of the memory device may use a data protocol for communicating the sideband information with the external device. Furthermore, systems and methods for receiving sideband information from multiple memory devices of a memory system are described to reduce latency and increase functionality of a memory system including such memory devices.

公开(公告)号：US11848067B2

公开(公告)日：2023-12-19

申请号：US17467800

申请日：2021-09-07

Applicant: Micron Technology, Inc.

Inventor： Joshua E. Alzheimer ,  Galaly Ahmad ,  Cory J. Kuffner

IPC: G11C29/36 ,  G11C29/10 ,  G11C29/42 ,  G11C29/12

CPC classification number: G11C29/36 ,  G11C29/10 ,  G11C29/1201 ,  G11C29/42 ,  G11C2029/3602

Abstract: An apparatus including a test validation circuit and associated systems and methods are disclosed herein. The apparatus may include a self-test circuit configured to implement at least a portion of a self-test process that determines operating conditions of the apparatus. The test validation circuit may be configured to generate a flag based on comparing (1) an input stream or a portion thereof associated with the self-test to (2) test data associated with the self-test. The flag may represent a validity associated with the implementation of the self-test process or the portion thereof.

公开(公告)号：US20230317193A1

公开(公告)日：2023-10-05

申请号：US17710601

申请日：2022-03-31

Applicant: Micron Technology, Inc.

Inventor： Joshua E. Alzheimer

IPC: G11C29/36 ,  G11C29/12 ,  G11C7/10

CPC classification number: G11C29/36 ,  G11C29/12005 ,  G11C29/12015 ,  G11C7/1096 ,  G11C7/1069 ,  G11C2029/3602

Abstract: A memory device may include sideband circuitry to provide additional functionality without interfering with normal operations of the memory device. The memory device may also include sideband pins to provide sideband information to an external device. The sideband information may include various digital or analog signals. In some cases, a sideband circuit of the memory device may use a data protocol for communicating the sideband information with the external device. Furthermore, systems and methods for receiving sideband information from multiple memory devices of a memory system are described to reduce latency and increase functionality of a memory system including such memory devices.