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    DUAL COMPRESSION IN MEMORY DEVICES
    1.
    发明申请
    DUAL COMPRESSION IN MEMORY DEVICES 有权

    公开(公告)号：US20250094047A1

    公开(公告)日：2025-03-20

    申请号：US18782539

    申请日：2024-07-24

    Applicant: Micron Technology, Inc.

    Inventor： Marco Sforzin ,  Rishabh Dubey ,  Daniele Balluchi ,  Danilo Caraccio ,  Emanuele Confalonieri ,  Nicola Del Gatto

    IPC: G06F3/06

    Abstract: A variety of applications can include a memory device implementing a dual compression scheme. A memory subsystem of the memory device can be arranged into multiple regions. A first region of the memory subsystem can be used to store non-compressible data. A second region can be used to store compressible data. The second region can have a first subregion and a second subregion. The first subregion can be used to accept compressible data as non-compressed data corresponding to a compression ratio being less than a threshold compression ratio. The second subregion can be used to accept compressed data corresponding to a compression ratio being greater than the threshold compression ratio. Additional apparatus, systems, and methods are disclosed.

    CONTROLLER FOR MANAGING METRICS AND TELEMETRY
    2.
    发明申请
    CONTROLLER FOR MANAGING METRICS AND TELEMETRY 有权

    公开(公告)号：US20250044980A1

    公开(公告)日：2025-02-06

    申请号：US18921891

    申请日：2024-10-21

    Applicant: Micron Technology, Inc.

    Inventor： Nicola Del Gatto ,  Federica Cresci ,  Emanuele Confalonieri

    IPC: G06F3/06

    Abstract: Systems, apparatuses, and methods related to a controller for managing metrics and telemetry are described. A controller includes a front end portion, a central controller portion, a back end portion, and a management unit. The central controller portion can include a cache to store data associated with the performance of the memory operations, metric logic configured to collect metrics related to performance of the memory operations, load telemetry logic configured to collect load telemetry associated with performance of the memory operations within a threshold time, and a storage area to store the collected metrics and the collected load telemetry. The management unit memory of the controller can store metrics and load telemetry associated with monitoring the characteristics of the memory controller, and based on the stored metrics and load telemetry, alter at least one characteristic of the computing system.

    Read Data Path
    3.
    发明申请
    Read Data Path 有权

    公开(公告)号：US20240427660A1

    公开(公告)日：2024-12-26

    申请号：US18670167

    申请日：2024-05-21

    Applicant: Micron Technology, Inc.

    Inventor： Nicola Del Gatto ,  Emanuele Confalonieri

    IPC: G06F11/10

    Abstract: Described apparatuses and methods relate to a read data path for a memory system. The memory system may include logic that receives data and associated metadata from a memory. The logic may perform a reliability check on the data using the associated metadata to determine if the data has an error. If the data is determined not to include an error, the data may be transmitted to a requestor. If the data is determined to include an error, however, a data recovery process may be initiated to recover the data. This may reduce a likelihood the memory system returns corrupted data to a requestor. The memory system may process a different read request at least partially in parallel with the data recovery process to increase throughput or reduce latency. In some cases, the data recovery process may involve one or more techniques related to redundant array of disks (RAID) technology.

    ROW TRACKING FOR ROW HAMMER MITIGATION
    4.
    发明公开
    ROW TRACKING FOR ROW HAMMER MITIGATION 审中-公开

    公开(公告)号：US20240071459A1

    公开(公告)日：2024-02-29

    申请号：US18237786

    申请日：2023-08-24

    Applicant: Micron Technology, Inc.

    Inventor： Emanuele Confalonieri ,  Yaw Fann ,  Yu-Sheng Hsu

    IPC: G11C11/406 ,  G06F3/06

    CPC classification number: G11C11/406 ,  G06F3/0623 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0683

    Abstract: A control mechanism may be implemented in a back-end of a memory sub-system to refresh rows of a memory device. Rows of the memory device can be refreshed based on a quantity of times the rows have been updated in a duration of time. Rows of the memory device can also be updated based on a duration of time between receipt of the activation command for the row and a pre-charge command for the row. Row of the memory device clan further be updated utilizing a pair of counters that implement a ping pong mechanism to retain data between different consecutive durations of time.

    DATA IDENTITY RECOGNITION FOR SEMICONDUCTOR DEVICES
    5.
    发明公开
    DATA IDENTITY RECOGNITION FOR SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20240061792A1

    公开(公告)日：2024-02-22

    申请号：US18235289

    申请日：2023-08-17

    Applicant: Micron Technology, Inc.

    Inventor： Emanuele Confalonieri ,  Paolo Amato ,  Daniele Balluchi ,  Marco Sforzin ,  Danilo Caraccio ,  Niccolò Izzo ,  Graziano Mirichigni ,  Massimiliano Patriarca

    IPC: G06F12/14 ,  G06F12/0804

    CPC classification number: G06F12/1458 ,  G06F12/0804

    Abstract: Systems, apparatuses, and methods related to data identity recognition for semiconductor devices are described. A system includes a host and a memory device coupled to the host via an interconnect bus. The host includes a host security manager configured to encrypt data of a command, perform a memory integrity check, allow access to memory of a memory device corresponding to an address of a command based on which entity associated with the host sent the command, generate security keys, program security keys into the memory device, program encryption ranges, or any combination thereof. The memory device includes a memory encryption manager and a memory device security manager. The memory device security manager is configured to detect whether a command was sent from a trusted domain of the host or non-trusted domain of the host and identify which entity associated with the host initiated the command.

    APPARATUS FOR REDUNDANT ARRAY OF INDEPENDENT DISKS
    6.
    发明公开
    APPARATUS FOR REDUNDANT ARRAY OF INDEPENDENT DISKS 审中-公开

    公开(公告)号：US20240004760A1

    公开(公告)日：2024-01-04

    申请号：US18216160

    申请日：2023-06-29

    Applicant: Micron Technology, Inc.

    Inventor： Paolo Amato ,  Daniele Balluchi ,  Danilo Caraccio ,  Emanuele Confalonieri ,  Marco Sforzin

    IPC: G06F11/10

    CPC classification number: G06F11/1076

    Abstract: A channel width can depend on a quantity of memory units (e.g., memory dice) that forms a channel as well as a size of the memory units. A memory system can operate with memory units configured to exchange (e.g., transfer to and/or from) data at a rate of smaller granularity that can provide more various options for channel widths, which can further allow a fine-tuned optimization of the memory system in association with its bandwidth and latency in transferring data from and/or to the memory units. The channels whose channel width is fine-tuned with such memory units can be further used to provide a reliability, availability, and serviceability (RAS) protection, such as a redundant array of independent disks (RAID) protection.

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