公开(公告)号：US09653143B2

公开(公告)日：2017-05-16

申请号：US15170785

申请日：2016-06-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： John David Porter ,  Gi-Hong Kim

IPC: G11C7/00 ,  G11C11/406 ,  G11C8/08 ,  G11C8/10 ,  G11C11/408 ,  G11C5/14 ,  G11C11/402

CPC classification number: G11C11/40615 ,  G11C5/147 ,  G11C8/08 ,  G11C8/10 ,  G11C11/402 ,  G11C11/406 ,  G11C11/4085 ,  G11C2211/4065 ,  G11C2211/4067

Abstract: Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of memory section control circuits. Each memory section control circuit is coupled to a respective one of the plurality of memory sections and includes a plurality of access line drivers, each of which includes a plurality of transistors having common coupled gates. During an operation of the apparatus a first voltage is provided to the commonly coupled gates of the transistors of at least some of the access line drivers of the memory section control circuit coupled to an active memory section and a second voltage is provided to the commonly coupled gates of the transistors of the access line drivers of the memory section control circuit coupled to an inactive memory section control circuit, wherein the first voltage is greater than the second voltage.

公开(公告)号：US20140078847A1

公开(公告)日：2014-03-20

申请号：US14084417

申请日：2013-11-19

Applicant: Micron Technology, Inc.

Inventor： John David Porter ,  Gi-Hong Kim

IPC: G11C5/14 ,  G11C11/402

CPC classification number: G11C11/40615 ,  G11C5/147 ,  G11C8/08 ,  G11C8/10 ,  G11C11/402 ,  G11C11/406 ,  G11C11/4085 ,  G11C2211/4065 ,  G11C2211/4067

Abstract: Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of memory section control circuits. Each memory section control circuit is coupled to a respective one of the plurality of memory sections and includes a plurality of access line drivers, each of which includes a plurality of transistors having common coupled gates. During an operation of the apparatus a first voltage is provided to the commonly coupled gates of the transistors of at least some of the access line drivers of the memory section control circuit coupled to an active memory section an and a second voltage is provided to the commonly coupled gates of the transistors of the access line drivers of the memory section control circuit coupled to an inactive memory section control circuit, wherein the first voltage is greater than the second voltage.

Abstract translation: 公开了设备，存储器部分控制电路和刷新存储器的方法。 示例性设备包括多个存储器部分和多个存储器部分控制电路。 每个存储器部分控制电路耦合到多个存储器部分中的相应一个，并且包括多个存取线驱动器，每个存取线驱动器包括具有公共耦合栅极的多个晶体管。 在装置的操作期间，第一电压被提供给耦合到有源存储器部分a的存储器部分控制电路的至少一些存取线驱动器的晶体管的共同耦合的栅极，并且第二电压被提供给共同的 存储器部分控制电路的存取线路驱动器的晶体管的耦合到非活动存储器部分控制电路的耦合栅极，其中第一电压大于第二电压。

公开(公告)号：US20140204689A1

公开(公告)日：2014-07-24

申请号：US14223647

申请日：2014-03-24

Applicant: Micron Technology, Inc.

Inventor： Gi-Hong Kim ,  John D. Porter

IPC: H03K17/16 ,  G11C11/419

CPC classification number: H03K17/162 ,  G11C7/1057 ,  G11C7/1096 ,  G11C7/12 ,  G11C8/08 ,  G11C8/10 ,  G11C11/419

Abstract: Apparatus and methods for driving a signal are disclosed. An example apparatus includes a pre-driver circuit and a driver circuit. The pre-driver circuit includes a step-down transistor and the driver circuit includes a pull-down transistor configured to be coupled to a reference voltage. In a first mode, the step-down transistor is configured to reduce a voltage provided to the pull-down transistor to less than a supply voltage, and in a second mode, the step-down transistor configured to provide the voltage of the supply voltage to the pull-down transistor. The pre-driver circuit of the example signal driver circuit may further include a step-up transistor configured to increase a voltage provided to a pull-up transistor of the driver circuit to greater than the reference voltage, and in the second mode, the step-up transistor configured to provide the voltage of the reference voltage to the pull-up transistor.

Abstract translation: 公开了用于驱动信号的装置和方法。 示例性设备包括预驱动器电路和驱动器电路。 预驱动器电路包括降压晶体管，并且驱动器电路包括被配置为耦合到参考电压的下拉晶体管。 在第一模式中，降压晶体管被配置为将提供给下拉晶体管的电压降低到小于电源电压，并且在第二模式中，降压晶体管被配置为提供电源电压 到下拉晶体管。 示例性信号驱动器电路的预驱动器电路还可以包括升压晶体管，其被配置为将提供给驱动器电路的上拉晶体管的电压增加到大于参考电压，并且在第二模式中，步骤 该晶体管被配置为向上拉晶体管提供参考电压的电压。

公开(公告)号：US08861296B2

公开(公告)日：2014-10-14

申请号：US14084417

申请日：2013-11-19

Applicant: Micron Technology, Inc.

Inventor： John David Porter ,  Gi-Hong Kim

IPC: G11C7/00 ,  G11C11/402 ,  G11C11/408 ,  G11C8/08 ,  G11C5/14 ,  G11C11/406 ,  G11C8/10

CPC classification number: G11C11/40615 ,  G11C5/147 ,  G11C8/08 ,  G11C8/10 ,  G11C11/402 ,  G11C11/406 ,  G11C11/4085 ,  G11C2211/4065 ,  G11C2211/4067

Abstract: Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of memory section control circuits. Each memory section control circuit is coupled to a respective one of the plurality of memory sections and includes a plurality of access line drivers, each of which includes a plurality of transistors having common coupled gates. During an operation of the apparatus a first voltage is provided to the commonly coupled gates of the transistors of at least some of the access line drivers of the memory section control circuit coupled to an active memory section and a second voltage is provided to the commonly coupled gates of the transistors of the access line drivers of the memory section control circuit coupled to an inactive memory section control circuit, wherein the first voltage is greater than the second voltage.

Abstract translation: 公开了设备，存储器部分控制电路和刷新存储器的方法。 示例性设备包括多个存储器部分和多个存储器部分控制电路。 每个存储器部分控制电路耦合到多个存储器部分中的相应一个，并且包括多个存取线驱动器，每个存取线驱动器包括具有公共耦合栅极的多个晶体管。 在装置的操作期间，将第一电压提供给耦合到有源存储器部分的存储器部分控制电路的至少一些存取线驱动器的晶体管的共同耦合的栅极，并且第二电压被提供给共同耦合的 存储器部分控制电路的存取线驱动器的晶体管的栅极耦合到非活动存储器部分控制电路，其中第一电压大于第二电压。

公开(公告)号：US20160276017A1

公开(公告)日：2016-09-22

申请号：US15170785

申请日：2016-06-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： John David Porter ,  Gi-Hong Kim

IPC: G11C11/406 ,  G11C11/408

CPC classification number: G11C11/40615 ,  G11C5/147 ,  G11C8/08 ,  G11C8/10 ,  G11C11/402 ,  G11C11/406 ,  G11C11/4085 ,  G11C2211/4065 ,  G11C2211/4067

Abstract: Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of memory section control circuits. Each memory section control circuit is coupled to a respective one of the plurality of memory sections and includes a plurality of access line drivers, each of which includes a plurality of transistors having common coupled gates. During an operation of the apparatus a first voltage is provided to the commonly coupled gates of the transistors of at least some of the access line drivers of the memory section control circuit coupled to an active memory section and a second voltage is provided to the commonly coupled gates of the transistors of the access line drivers of the memory section control circuit coupled to an inactive memory section control circuit, wherein the first voltage is greater than the second voltage.

公开(公告)号：US09368184B2

公开(公告)日：2016-06-14

申请号：US14505717

申请日：2014-10-03

Applicant: Micron Technology, Inc.

Inventor： John David Porter ,  Gi-Hong Kim

IPC: G11C7/00 ,  G11C11/402 ,  G11C8/08 ,  G11C8/10 ,  G11C11/406 ,  G11C11/408 ,  G11C5/14

CPC classification number: G11C11/40615 ,  G11C5/147 ,  G11C8/08 ,  G11C8/10 ,  G11C11/402 ,  G11C11/406 ,  G11C11/4085 ,  G11C2211/4065 ,  G11C2211/4067

Abstract: Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of memory section control circuits. Each memory section control circuit is coupled to a respective one of the plurality of memory sections and includes a plurality of access line drivers, each of which includes a plurality of transistors having common coupled gates. During an operation of the apparatus a first voltage is provided to the commonly coupled gates of the transistors of at least some of the access line drivers of the memory section control circuit coupled to an active memory section and a second voltage is provided to the commonly coupled gates of the transistors of the access line drivers of the memory section control circuit coupled to an inactive memory section control circuit, wherein the first voltage is greater than the second voltage.

公开(公告)号：US09054700B2

公开(公告)日：2015-06-09

申请号：US14223647

申请日：2014-03-24

Applicant: Micron Technology, Inc.

Inventor： Gi-Hong Kim ,  John D. Porter

IPC: G11C8/00 ,  G11C11/34 ,  H03K17/16 ,  G11C7/10 ,  G11C7/12 ,  G11C8/08 ,  G11C8/10 ,  G11C11/419

CPC classification number: H03K17/162 ,  G11C7/1057 ,  G11C7/1096 ,  G11C7/12 ,  G11C8/08 ,  G11C8/10 ,  G11C11/419

Abstract: Apparatus and methods for driving a signal are disclosed. An example apparatus includes a pre-driver circuit and a driver circuit. The pre-driver circuit includes a step-down transistor and the driver circuit includes a pull-down transistor configured to be coupled to a reference voltage. In a first mode, the step-down transistor is configured to reduce a voltage provided to the pull-down transistor to less than a supply voltage, and in a second mode, the step-down transistor configured to provide the voltage of the supply voltage to the pull-down transistor. The pre-driver circuit of the example signal driver circuit may further include a step-up transistor configured to increase a voltage provided to a pull-up transistor of the driver circuit to greater than the reference voltage, and in the second mode, the step-up transistor configured to provide the voltage of the reference voltage to the pull-up transistor.

Abstract translation: 公开了用于驱动信号的装置和方法。 示例性设备包括预驱动器电路和驱动器电路。 预驱动器电路包括降压晶体管，并且驱动器电路包括被配置为耦合到参考电压的下拉晶体管。 在第一模式中，降压晶体管被配置为将提供给下拉晶体管的电压降低到小于电源电压，并且在第二模式中，降压晶体管被配置为提供电源电压 到下拉晶体管。 示例性信号驱动器电路的预驱动器电路还可以包括升压晶体管，其被配置为将提供给驱动器电路的上拉晶体管的电压增加到大于参考电压，并且在第二模式中，步骤 该晶体管被配置为向上拉晶体管提供参考电压的电压。

公开(公告)号：US20150023121A1

公开(公告)日：2015-01-22

申请号：US14505717

申请日：2014-10-03

Applicant: Micron Technology, Inc.

Inventor： John David Porter ,  Gi-Hong Kim

IPC: G11C11/402 ,  G11C8/10 ,  G11C8/08 ,  G11C5/14 ,  G11C11/408

CPC classification number: G11C11/40615 ,  G11C5/147 ,  G11C8/08 ,  G11C8/10 ,  G11C11/402 ,  G11C11/406 ,  G11C11/4085 ,  G11C2211/4065 ,  G11C2211/4067

Abstract: Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of memory section control circuits. Each memory section control circuit is coupled to a respective one of the plurality of memory sections and includes a plurality of access line drivers, each of which includes a plurality of transistors having common coupled gates. During an operation of the apparatus a first voltage is provided to the commonly coupled gates of the transistors of at least some of the access line drivers of the memory section control circuit coupled to an active memory section and a second voltage is provided to the commonly coupled gates of the transistors of the access line drivers of the memory section control circuit coupled to an inactive memory section control circuit, wherein the first voltage is greater than the second voltage.

Abstract translation: 公开了设备，存储器部分控制电路和刷新存储器的方法。 示例性设备包括多个存储器部分和多个存储器部分控制电路。 每个存储器部分控制电路耦合到多个存储器部分中的相应一个，并且包括多个存取线驱动器，每个存取线驱动器包括具有公共耦合栅极的多个晶体管。 在装置的操作期间，将第一电压提供给耦合到有源存储器部分的存储器部分控制电路的至少一些存取线驱动器的晶体管的共同耦合的栅极，并且第二电压被提供给共同耦合的 存储器部分控制电路的存取线驱动器的晶体管的栅极耦合到非活动存储器部分控制电路，其中第一电压大于第二电压。