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公开(公告)号：US11721396B2
公开(公告)日：2023-08-08
申请号：US17012442
申请日：2020-09-04
发明人： Violante Moschiano , Purval S. Sule , Han Liu , Andrea D'Alessandro , Pranav Kalavade , Han Zhao , Shantanu Rajwade
IPC分类号： G11C16/12 , G11C11/4074 , G11C16/04 , G11C16/34 , G11C5/06
CPC分类号： G11C16/12 , G11C5/063 , G11C11/4074 , G11C16/0483 , G11C16/3427
摘要： Memories having a controller configured to perform methods during programming operations including apply a first voltage level to a data line selectively connected to a selected memory cell selected, apply a lower second voltage level to a select gate connected between the data line and the memory cell, decrease the voltage level applied to the data line from the first voltage level to a third voltage level while continuing to apply the second voltage level to the select gate, increase the voltage level applied to the select gate from the second voltage level to a fourth voltage level after the voltage level of the data line settles to the third voltage level, and apply a programming voltage to the memory cell after increasing the voltage level applied to the select gate to the fourth voltage level.
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公开(公告)号：US10482974B1
公开(公告)日：2019-11-19
申请号：US16106185
申请日：2018-08-21
发明人： Violante Moschiano , Purval S. Sule , Han Liu , Andrea D'Alessandro , Pranav Kalavade , Han Zhao , Shantanu Rajwade
摘要： Methods include applying a first voltage level to first and second data lines while applying a second, lower, voltage level to first and second select gates connected between the data lines and respective strings of memory cells; decreasing a voltage level of the first data line to a third voltage level; increasing a voltage level of the first select gate to a fourth voltage level; applying a fifth voltage level, higher than the first voltage level, to first and second access lines coupled to memory cells of the strings of memory cells; and increasing a voltage level of the first access line to a sixth voltage level.
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公开(公告)号：US10777277B2
公开(公告)日：2020-09-15
申请号：US16655826
申请日：2019-10-17
发明人： Violante Moschiano , Purval S. Sule , Han Liu , Andrea D'Alessandro , Pranav Kalavade , Han Zhao , Shantanu Rajwade
IPC分类号： G11C16/12 , G11C11/4074 , G11C16/04 , G11C16/34 , G11C5/06
摘要： Memories having a controller configured to perform methods during programming operations including applying a first voltage level to first and second data lines while applying a second, lower, voltage level to first and second select gates connected between the data lines and respective strings of memory cells; decreasing a voltage level of the first data line to a third voltage level; increasing a voltage level of the first select gate to a fourth voltage level; applying a fifth voltage level, higher than the first voltage level, to first and second access lines coupled to memory cells of the strings of memory cells; and increasing a voltage level of the first access line to a sixth voltage level.
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公开(公告)号：US20200066350A1
公开(公告)日：2020-02-27
申请号：US16655826
申请日：2019-10-17
发明人： Violante Moschiano , Purval S. Sule , Han Liu , Andrea D'Alessandro , Pranav Kalavade , Han Zhao , Shantanu Rajwade
IPC分类号： G11C16/12 , G11C16/34 , G11C11/4074 , G11C5/06 , G11C16/04
摘要： Memories having a controller configured to perform methods during programming operations including applying a first voltage level to first and second data lines while applying a second, lower, voltage level to first and second select gates connected between the data lines and respective strings of memory cells; decreasing a voltage level of the first data line to a third voltage level; increasing a voltage level of the first select gate to a fourth voltage level; applying a fifth voltage level, higher than the first voltage level, to first and second access lines coupled to memory cells of the strings of memory cells; and increasing a voltage level of the first access line to a sixth voltage level.
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