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公开(公告)号：US11698725B2
公开(公告)日：2023-07-11
申请号：US17452468
申请日：2021-10-27
IPC分类号： G06F3/06 , G06F13/16 , G06F13/42 , G11C16/26 , G11C16/30 , G11C8/12 , G11C11/56 , G11C16/08 , G11C13/00 , G11C16/04
CPC分类号： G06F3/0604 , G06F3/0629 , G06F3/0673 , G06F13/16 , G06F13/42 , G11C8/12 , G11C11/5642 , G11C16/08 , G11C16/26 , G11C16/30 , G11C13/0004 , G11C13/004 , G11C13/0038 , G11C16/0483 , G11C2207/2209
摘要： Apparatuses and methods for performing concurrent memory access operations for multiple memory planes are disclosed herein. An example method may include receiving first and second command and address pairs associated with first and second plane, respectively, of a memory. The method may further include, responsive to receiving the first and second command and address pairs, providing a first and second read voltages based on first and second page type determined from the first and second command and address pair. The method may further include configuring a first GAL decoder circuit to provide one of the first read voltage or a pass voltage on each GAL of a first GAL bus. The method may further include configuring a second GAL decoder circuit to provide one of the second read level voltage signal or the pass voltage signal on each GAL of a second GAL bus coupled to the second memory plane.
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公开(公告)号：US20220155958A1
公开(公告)日：2022-05-19
申请号：US17452468
申请日：2021-10-27
摘要： Apparatuses and methods for performing concurrent memory access operations for multiple memory planes are disclosed herein. An example method may include receiving first and second command and address pairs associated with first and second plane, respectively, of a memory. The method may further include, responsive to receiving the first and second command and address pairs, providing a first and second read voltages based on first and second page type determined from the first and second command and address pair. The method may further include configuring a first GAL decoder circuit to provide one of the first read voltage or a pass voltage on each GAL of a first GAL bus. The method may further include configuring a second GAL decoder circuit to provide one of the second read level voltage signal or the pass voltage signal on each GAL of a second GAL bus coupled to the second memory plane.
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公开(公告)号：US11029861B2
公开(公告)日：2021-06-08
申请号：US16543743
申请日：2019-08-19
发明人： Shafqat Ahmed , Khaled Hasnat , Pranav Kalavade , Krishna Parat , Aaron Yip , Mark A. Helm , Andrew Bicksler
IPC分类号： G06F3/06 , G11C16/24 , G11C16/26 , G11C16/04 , G06F12/0804 , G06F13/28 , G06F12/0846
摘要： Memory devices might be configured to perform methods including reading a first page of memory cells and flag data wherein the flag data indicates whether a second page of memory cells adjacent to the first page is programmed, and determining from the flag data whether to re-read the first page of memory cells with an adjusted read voltage; performing a sense operation on memory cells coupled to first data lines of a first array of memory cells and memory cells coupled to data lines of a second array of memory cells, and determining a program indication of memory cells coupled to second data lines from the sense operation performed on the memory cells coupled to the data lines of the second array of memory cells; and/or programming memory cells coupled to first data lines in a first array of memory cells, and programming memory cells coupled to second data lines in the first array of memory cells while programming memory cells coupled to data lines in a second array of memory cells with flag data indicative of the memory cells coupled to the second data lines in the first array of memory cells being programmed.
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公开(公告)号：US20180217782A1
公开(公告)日：2018-08-02
申请号：US15940351
申请日：2018-03-29
CPC分类号： G06F3/0656 , G06F3/061 , G06F3/0679 , G11C7/1084 , G11C11/5628 , G11C16/10 , G11C16/32
摘要： Apparatuses and methods for performing buffer operations in memory are provided. One example method can include storing second page data and third page data on a buffer while programming first page data during a first pass programming operation and programming the second page data and the third page data from the buffer to the array of memory cells during a second pass programming operation.
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公开(公告)号：US20180143784A1
公开(公告)日：2018-05-24
申请号：US15359306
申请日：2016-11-22
CPC分类号： G06F3/0656 , G06F3/061 , G06F3/0679 , G11C7/1084 , G11C11/5628 , G11C16/10 , G11C16/32
摘要： Apparatuses and methods for performing buffer operations in memory are provided. One example method can include storing second page data and third page data on a buffer while programming first page data during a first pass programming operation and programming the second page data and the third page data from the buffer to the array of memory cells during a second pass programming operation.
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6.发明申请公开(公告)号：US20180136845A1
公开(公告)日：2018-05-17
申请号：US15854622
申请日：2017-12-26
CPC分类号： G06F3/0604 , G06F3/0629 , G06F3/0673 , G06F13/16 , G06F13/42 , G11C8/12 , G11C11/5642 , G11C13/0004 , G11C13/0038 , G11C13/004 , G11C16/0483 , G11C16/08 , G11C16/26 , G11C16/30 , G11C2207/2209
摘要： Apparatuses and methods for performing concurrent memory access operations for multiple memory planes are disclosed herein. An example method may include receiving first and second command and address pairs associated with first and second plane, respectively, of a memory. The method may further include, responsive to receiving the first and second command and address pairs, providing a first and second read voltages based on first and second page type determined from the first and second command and address pair. The method may further include configuring a first GAL decoder circuit to provide one of the first read voltage or a pass voltage on each GAL of a first GAL bus. The method may further include configuring a second GAL decoder circuit to provide one of the second read level voltage signal or the pass voltage signal on each GAL of a second GAL bus coupled to the second memory plane.
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公开(公告)号：US20160307622A1
公开(公告)日：2016-10-20
申请号：US15189178
申请日：2016-06-22
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3427
摘要： Methods of operating a memory include applying a multi-step pass voltage to a plurality of memory cells selected for a programming operation, applying a programming pulse to the plurality of memory cells selected for the programming operation after applying a voltage level of a particular step of the multi-step pass voltage to the plurality of memory cells selected for the programming operation, applying a particular voltage level to any data lines coupled to a first subset of memory cells of the plurality of memory cells selected for the programming operation prior to applying a voltage level of a certain step of the multi-step pass voltage, and applying the particular voltage level to any data lines coupled to a second subset of memory cells of the plurality of memory cells selected for the programming operation only after applying the voltage level of the certain step of the multi-step pass voltage.
摘要翻译： 操作存储器的方法包括对选择用于编程操作的多个存储器单元施加多级通过电压，在将编程脉冲施加到编程操作所选择的多个存储器单元之后，施加特定步骤的电压电平 向被选择用于编程操作的多个存储器单元的多步通过电压，将特定电压电平施加到耦合到在应用编程操作之前被选择用于编程操作的多个存储器单元中的存储器单元的第一子集的任何数据线 多级通过电压的某一步骤的电压电平，并且将特定电压电平施加到仅在施加电压电平之后耦合到被选择用于编程操作的多个存储器单元的存储器单元的第二子集的任何数据线 多步通过电压的一定步骤。
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公开(公告)号：US20160019949A1
公开(公告)日：2016-01-21
申请号：US14334946
申请日：2014-07-18
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3427
摘要： Memories and methods for programming memories with multi-level pass signals are provided. One method includes programming cells of the memory selected to be programmed to a particular target data state of the memory, using program disturb to program cells of the memory selected to be programmed to target data states that are lower than the particular target data state while programming cells of the memory selected to be programmed to the particular target data state, and boosting a channel voltage for cells of the memory selected to be programmed to the target data states that are lower than the particular target data state. Boosting may include using a multi-step pass signal.
摘要翻译： 提供了用于编程具有多级通过信号的存储器的存储器和方法。 一种方法包括将选择要编程的存储器的单元编程为存储器的特定目标数据状态，使用程序干扰来编程选择要编程的存储器的单元，以在编程期间将目标数据状态低于特定目标数据状态 将存储器的单元选择为被编程到特定目标数据状态，以及将选择要编程的存储器的单元的通道电压提升到低于特定目标数据状态的目标数据状态。 升压可能包括使用多步通过信号。
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公开(公告)号：US10777277B2
公开(公告)日：2020-09-15
申请号：US16655826
申请日：2019-10-17
发明人： Violante Moschiano , Purval S. Sule , Han Liu , Andrea D'Alessandro , Pranav Kalavade , Han Zhao , Shantanu Rajwade
IPC分类号： G11C16/12 , G11C11/4074 , G11C16/04 , G11C16/34 , G11C5/06
摘要： Memories having a controller configured to perform methods during programming operations including applying a first voltage level to first and second data lines while applying a second, lower, voltage level to first and second select gates connected between the data lines and respective strings of memory cells; decreasing a voltage level of the first data line to a third voltage level; increasing a voltage level of the first select gate to a fourth voltage level; applying a fifth voltage level, higher than the first voltage level, to first and second access lines coupled to memory cells of the strings of memory cells; and increasing a voltage level of the first access line to a sixth voltage level.
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公开(公告)号：US10043574B2
公开(公告)日：2018-08-07
申请号：US15907826
申请日：2018-02-28
摘要： Methods of operating a memory include applying a first voltage level to control gates of a plurality of memory cells selected to be programmed while applying a second voltage level to a respective data line for each memory cell of the plurality of memory cells; increasing the voltage level applied to the respective data line for memory cells of a first subset of memory cells to a third voltage level then increasing the voltage level applied to the control gates of the plurality of memory cells to a fourth voltage level; increasing the voltage level applied to the respective data line for each memory cell of a second subset of memory cells of the plurality of memory cells to a fifth voltage level then; and after increasing the voltage level applied to the respective data line for each memory cell of the second subset of memory cells to the fifth voltage level, increasing the voltage level applied to the control gates of the plurality of memory cells to a sixth voltage level.
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