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公开(公告)号:US11764571B2
公开(公告)日:2023-09-19
申请号:US17071562
申请日:2020-10-15
发明人: Haruka Momota , Takashi Ishihara
CPC分类号: H02H9/046 , H01L27/0248 , H01L27/0296
摘要: Disclosed herein is an apparatus that includes a first power ESD protection circuit arranged in a first circuit area; a plurality of data I/O circuits arranged in a second circuit area adjacent to the first circuit area in a first direction; a plurality of data I/O terminals arranged in the second circuit area, each of the plurality of data I/O terminals being coupled to an associated one of the plurality of data I/O circuits; a plurality of first power terminals arranged in the second circuit area; and a first power line extending in the first direction, the first power line coupling the plurality of first power terminals to the first power ESD protection circuit.
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公开(公告)号:US20220123550A1
公开(公告)日:2022-04-21
申请号:US17071562
申请日:2020-10-15
发明人: Haruka Momota , Takashi Ishihara
摘要: Disclosed herein is an apparatus that includes a first power ESD protection circuit arranged in a first circuit area; a plurality of data I/O circuits arranged in a second circuit area adjacent to the first circuit area in a first direction; a plurality of data I/O terminals arranged in the second circuit area, each of the plurality of data I/O terminals being coupled to an associated one of the plurality of data I/O circuits; a plurality of first power terminals arranged in the second circuit area; and a first power line extending in the first direction, the first power line coupling the plurality of first power terminals to the first power ESD protection circuit.
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公开(公告)号:US20230360688A1
公开(公告)日:2023-11-09
申请号:US17740200
申请日:2022-05-09
发明人: Kazuhiro Yoshida , Go Takashima , Haruka Momota
IPC分类号: G11C11/4074 , H01L27/108
CPC分类号: G11C11/4074 , H01L27/10897
摘要: Disclosed herein is an apparatus that includes: a semiconductor substrate including first and second source regions coupled to a first power supply line and first and second drain regions coupled to a second power supply line, the first drain region being arranged between the first and second source regions, the second source region being arranged between the first and second drain regions; and gate electrodes including a first gate electrode arranged between the first source region and the first drain region, a second gate electrode arranged between the first drain region and the second source region, and a third gate electrode arranged between the second source region and the second drain region. The first and third gate electrodes are supplied with a first control signal. The second gate electrode is supplied with a second control signal.
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公开(公告)号:US11948620B2
公开(公告)日:2024-04-02
申请号:US17740200
申请日:2022-05-09
发明人: Kazuhiro Yoshida , Go Takashima , Haruka Momota
IPC分类号: G11C11/10 , G11C11/4074 , H10B12/00
CPC分类号: G11C11/4074 , H10B12/50
摘要: Disclosed herein is an apparatus that includes: a semiconductor substrate including first and second source regions coupled to a first power supply line and first and second drain regions coupled to a second power supply line, the first drain region being arranged between the first and second source regions, the second source region being arranged between the first and second drain regions; and gate electrodes including a first gate electrode arranged between the first source region and the first drain region, a second gate electrode arranged between the first drain region and the second source region, and a third gate electrode arranged between the second source region and the second drain region. The first and third gate electrodes are supplied with a first control signal. The second gate electrode is supplied with a second control signal.
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公开(公告)号:US20230187289A1
公开(公告)日:2023-06-15
申请号:US17550741
申请日:2021-12-14
发明人: Haruka Momota , Koji Yasumori , Keizo Kawakita
IPC分类号: H01L21/66 , H01L21/768 , H01L23/528 , H01L23/525
CPC分类号: H01L22/32 , H01L21/76802 , H01L23/528 , H01L23/5256 , H01L27/10897
摘要: An apparatus includes an active region; a scribe region surrounding the active region; a test component in the scribe region; a pad electrode in the active region; and a power supply wiring of an upper wiring layer in the active region, the power supply wiring extending between the test component and the pad electrode; and an interconnection structure coupling the test component and the pad electrode across a border between the active region and the scribe region, the interconnection structure including a wiring portion of a lower wiring layer crossing the power supply wiring.
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